# frv testcase for thi $ICCi_2,$GRi,$GRj# mach: all	.include "testutils.inc"	start	.global thithi:	and_spr_immed	-4081,tbr		; clear tbr.tt	set_gr_spr	tbr,gr7	inc_gr_immed	2112,gr7		; address of exception handler	set_bctrlr_0_0	gr7	; bctrlr 0,0	set_spr_immed	128,lcr	set_gr_immed	0,gr7	set_gr_immed	4,gr8	set_psr_et	1	set_spr_addr	ok0,lr	set_icc		0x0 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	failok0:	set_spr_addr	bad,lr	set_icc		0x1 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	ok2,lr	set_icc		0x2 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	failok2:	set_spr_addr	bad,lr	set_icc		0x3 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0x4 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0x5 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0x6 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0x7 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	ok8,lr	set_icc		0x8 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	failok8:	set_spr_addr	bad,lr	set_icc		0x9 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_psr_et	1	set_spr_addr	oka,lr	set_icc		0xa 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	failoka:	set_spr_addr	bad,lr	set_icc		0xb 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0xc 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0xd 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0xe 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	set_spr_addr	bad,lr	set_icc		0xf 0	thi 		icc0,gr7,gr8	; should branch to tbr + (128 + 4)*16	passbad:	fail