-- Copyright 2007 Actel Corporation. All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN                              
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED                              
-- IN ADVANCE IN WRITING.                                                                        
-- Revision: 1.0 
-- History:  Revision   Date                Author              Remarks.
-- SVN Revision Information:
-- SVN $Revision: $                                   
library ieee;
use IEee.std_logiC_1164.all;
library fusion;
use fusion.all;
entity CCALIBili1 is
port (CCALIBOII1: in STD_LOgic_vectoR(8 downto 0);
CCALIBlii1: out STd_logic_vECTOR(8 downto 0);
CCALIBiii1,CCALIBo0i1: in Std_logic;
CCALIBl0I1: in std_logiC_VECTor(8 downto 0);
CCALIBi0i1: in STD_LOGIc_vector(8 downto 0);
CCALIBo1i1,CCALIBl1i1: in std_loGIC);
end CCALIBIli1;

architecture CCALIBLL of CCALIBILi1 is

component inv
port (A: in STD_LOGic := 'U';
Y: out std_logiC);
end component;

component ram4k9
generic (memoryFILE: STRING := "");
port (addra11,addra10,ADdra9,ADDRA8,addRA7,addra6,ADDRA5,addra4,ADDRA3,addra2,adDRA1,addRA0,ADDRB11,addrb10,addrb9,addrb8,addrb7,Addrb6,ADDRB5,aDDRB4,addrb3,ADDrb2,addRB1,addrb0,diNA8,DINa7,dina6,dina5,dina4,dina3,DINa2,DINA1,DINa0,DINB8,dINB7,dinb6,DINB5,diNB4,Dinb3,DINB2,dinb1,dinb0,wiDTHA0,widtha1,widthb0,wIDTHB1,PIPEA,PIPEB,WMODEA,WMODeb,BLKA,blkb,WENA,wenb,CLKA,clkb,RESET: in STd_logic := 'U';
Douta8,douTA7,DOUTA6,Douta5,douta4,douta3,douta2,douta1,douta0,doutb8,doutb7,doutb6,DOUTB5,dOUTB4,doutb3,DOUTB2,doUTB1,DOutb0: out STd_logic);
end component;

component vcc
port (y: out std_LOGIC);
end component;

component Gnd
port (Y: out std_logic);
end component;

signal CCALIBI1LOL,CCALIBOOIOL,CCALIBLOIOl,CCALIBIOIol: stD_LOGIC;

begin
CCALIBOLIOL: vCC
port map (y => CCALIBloiOL);
CCALIBllIOL: gnd
port map (Y => CCALIBioioL);
CCALIBILIOL: inv
port map (a => CCALIBo0i1,
y => CCALIBoOIOL);
CCALIBoiioL: ram4k9
port map (addrA11 => CCALIBioioL,
aDDRA10 => CCALIBIoiol,
addra9 => CCALIBioiOL,
ADDRA8 => CCALIBL0I1(8),
ADDRA7 => CCALIBL0I1(7),
addra6 => CCALIBl0i1(6),
addra5 => CCALIBl0i1(5),
addrA4 => CCALIBl0I1(4),
addra3 => CCALIBL0I1(3),
addRA2 => CCALIBL0i1(2),
ADDRA1 => CCALIBl0i1(1),
Addra0 => CCALIBl0i1(0),
adDRB11 => CCALIBioiol,
ADDRB10 => CCALIBIOIOl,
addrb9 => CCALIBIOIOL,
addrb8 => CCALIBi0i1(8),
ADDRB7 => CCALIBI0I1(7),
aDDRB6 => CCALIBi0i1(6),
ADDRB5 => CCALIBI0I1(5),
ADdrb4 => CCALIBI0i1(4),
ADDRB3 => CCALIBi0i1(3),
addrb2 => CCALIBI0I1(2),
ADdrb1 => CCALIBI0i1(1),
ADDRB0 => CCALIBi0i1(0),
DINA8 => CCALIBOIi1(8),
dina7 => CCALIBoii1(7),
dina6 => CCALIBoii1(6),
dina5 => CCALIBoii1(5),
dina4 => CCALIBoii1(4),
Dina3 => CCALIBoii1(3),
dINA2 => CCALIBoii1(2),
dina1 => CCALIBOII1(1),
dina0 => CCALIBoii1(0),
Dinb8 => CCALIBIOIOL,
DINb7 => CCALIBIOIOL,
dinb6 => CCALIBIOIOL,
Dinb5 => CCALIBIOiol,
dinb4 => CCALIBioiol,
DInb3 => CCALIBIOiol,
DINB2 => CCALIBioIOL,
DINB1 => CCALIBiOIOL,
DINB0 => CCALIBioioL,
widtha0 => CCALIBloiOL,
widtHA1 => CCALIBlOIOL,
widthb0 => CCALIBloiol,
WIDTHB1 => CCALIBLOIOL,
pipea => CCALIBioiOL,
Pipeb => CCALIBIOIOl,
wmODEA => CCALIBIOIol,
wmodEB => CCALIBioiol,
blKA => CCALIBi1loL,
blkB => CCALIBOOIol,
wena => CCALIBioiol,
wenb => CCALIBloiol,
clka => CCALIBo1i1,
CLKB => CCALIBL1i1,
RESET => CCALIBLOIOL,
Douta8 => open ,
douTA7 => open ,
douta6 => open ,
douta5 => open ,
DOUTA4 => open ,
douta3 => open ,
douta2 => open ,
DOUTA1 => open ,
douta0 => open ,
doutb8 => CCALIBLIi1(8),
douTB7 => CCALIBlII1(7),
dOUTB6 => CCALIBlii1(6),
doutb5 => CCALIBlii1(5),
DOUTB4 => CCALIBlii1(4),
DOUTB3 => CCALIBLII1(3),
DOutb2 => CCALIBlii1(2),
DOUtb1 => CCALIBlII1(1),
DOutb0 => CCALIBlii1(0));
CCALIBliiol: inv
port map (A => CCALIBIII1,
Y => CCALIBi1loL);
end CCALIBll;