-- Copyright 2007 Actel Corporation. All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN                              
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED                              
-- IN ADVANCE IN WRITING.                                                                        
-- Revision: 4.1 
--   Revision   Date        Author   Remarks
-- SVN Revision Information:
-- SVN $Revision: $                                   
library Ieee;
use ieeE.stD_logic_1164.all;
use iEEE.Std_logic_UNSIGNEd.all;
entity caLIBIP_Clram is
generic (g_debug: INTEGer := 0;
g_USE_SRAm_tiles: INTEGer := 0); port (s_cLK_IN: in STD_Logic;
S_reset_n_IN: in STd_logic;
S_INIT_clk_in: in STd_logic;
sv_INIT_DAta_in: in STd_logic_veCTOR(8 downto 0);
sv_iNIT_ADDr_in: in STD_LOgic_vectoR(10 downto 0);
s_init_ROM_WEN_in: in sTD_LOGIc;
s_init_COEFF_wen_in: in std_LOGIC;
S_INIT_done_in: in Std_logic;
s_aDC_CH_Error_ouT: out std_logiC;
s_adC_START_in: in Std_logic;
sV_CH_NUmber_in: in STD_LOGic_vectoR(4 downto 0);
sv_m_out: out std_logiC_VECTor(10 downto 0);
SV_c_out: out std_lOGIC_VEctor(7 downto 0));
end entity CAlibip_clrAM;

architecture behavIORAL of Calibip_clrAM is

component CCALIBili1 is
port (CCALIBoii1: in std_loGIC_VECtor(8 downto 0);
CCALIBlii1: out Std_logic_VECTOR(8 downto 0);
CCALIBiii1,CCALIBo0i1: in std_logiC;
CCALIBl0i1: in Std_logic_VECTOR(8 downto 0);
CCALIBi0i1: in STD_logic_veCTOR(8 downto 0);
CCALIBo1i1,CCALIBl1i1: in stD_LOGIC);
end component;

signal CCALIBI1I1: STD_LOGic_vectoR(4 downto 0);

signal CCALIBoO01: Std_logic_VECTOR(4 downto 0);

signal CCALIBlo01: STD_LOgic_vectOR(4 downto 0);

signal CCALIBIO01: std_loGIC_VECtor(4 downto 0);

signal CCALIBol01: std_logIC_VECTor(5 downto 0);

signal CCALIBll01: std_logiC;

signal CCALIBIl01: std_LOGIC;

signal CCALIBoi01: stD_LOGIC_vector(8 downto 0);

signal CCALIBli01: Std_logic_VECTOR(8 downto 0);

signal CCALIBii01: stD_LOGIC;

signal CCALIBo001: sTD_LOGIc;

signal CCALIBL001: std_lOGIC_VEctor(8 downto 0);

signal CCALIBi001: std_loGIC;

signal CCALIBo101: std_loGIC;

signal CCALIBl101: std_loGIC;

signal CCALIBI101: STD_logic;

signal CCALIBoo11: std_logiC_VECTOr(8 downto 0);

begin
CCALIBlo11:
if (g_use_srAM_TILEs = 0)
generate
CCALIBio11: CCALIBili1
port map (CCALIBO1I1 => S_clk_in,
CCALIBl1I1 => s_clK_IN,
CCALIBl0i1 => CCALIBoi01,
CCALIBI0I1 => CCALIBli01,
CCALIBiII1 => CCALIBii01,
CCALIBO0I1 => CCALIBO001,
CCALIBoii1 => SV_INit_data_IN,
CCALIBlii1 => CCALIBl001);
end generate CCALIBlo11;
CCALIBOL11:
if (not (G_USE_Sram_tileS = 0))
generate
end generate CCALIBOL11;
CCALIBii01 <= S_INIT_rom_wen_IN or CCALIBI001;
CCALIBi001 <= s_inIT_COEFf_wen_iN and CCALIBl101
and CCALIBo101;
CCALIBl101 <= '1' when (CCALIBi1I1(4 downto 0) /= "11111") else
'0';
CCALIBo101 <= '1' when (Sv_init_adDR_IN(10 downto 2) = CCALIBl001(8 downto 0)) else
'0';
CCALIBi101 <= s_init_ROM_Wen_in and not (s_init_coEFF_WEn_in);
CCALIBoi01(8 downto 0) <= sv_iNIT_ADDr_in(8 downto 0) when ((CCALIBi101)) = '1' else
("10"&CCALIBi1i1(4 downto 0)&SV_init_addr_IN(1 downto 0));
process (S_CLK_in,S_reset_n_iN)
begin
if (S_Reset_n_in = '0') then
CCALIBi1i1 <= "00000";
elsif (S_CLK_In'EVENT and s_CLK_IN = '1') then
CCALIBi1i1 <= CCALIBOO01;
end if;
end process;
CCALIBo001 <= '1';
process (S_clk_in,s_RESET_n_in)
begin
if (S_REset_n_in = '0') then
CCALIBOl01 <= "000000";
elsif (s_clk_in'evenT and S_clk_in = '1') then
CCALIBol01 <= (CCALIBol01(4 downto 0)&s_adc_staRT_IN);
end if;
end process;
CCALIBli01(8 downto 0) <= CCALIBoo11(8 downto 0) when ((s_init_donE_IN)) = '1' else
("0000"&CCALIBOO01(4 downto 0));
CCALIBoo11(8 downto 0) <= ("0100"&CCALIBio01(4 downto 0)) when ((CCALIBol01(0))) = '1' else
("10"&CCALIBLo01(4 downto 0)&CCALIBol01(4 downto 3));
process (s_clk_iN,S_RESEt_n_in)
begin
if (S_RESEt_n_in = '0') then
CCALIBoo01 <= "00000";
CCALIBil01 <= '0';
elsif (s_clk_iN'event and S_CLK_in = '1') then
if (CCALIBIL01 = '1') then
CCALIBoo01 <= CCALIBOO01+"00001";
end if;
if (sv_init_ADDR_in(1 downto 0) = "01") then
CCALIBIL01 <= CCALIBI001;
else
CCALIBil01 <= '0';
end if;
end if;
end process;
process (s_CLK_IN,S_reset_n_iN)
begin
if (S_reset_n_IN = '0') then
CCALIBio01 <= "00000";
elsif (s_clk_in'event and s_cLK_IN = '1') then
if (S_ADC_start_iN = '1') then
CCALIBIO01 <= sv_CH_NUMBer_in;
end if;
end if;
end process;
process (S_clk_in,s_resET_N_IN)
begin
if (S_RESet_n_in = '0') then
CCALIBLO01 <= "00000";
elsif (S_clk_in'event and s_CLK_IN = '1') then
if (CCALIBOL01(1) = '1') then
CCALIBLo01 <= CCALIBL001(4 downto 0);
end if;
end if;
end process;
process (s_clk_in,s_RESET_n_in)
begin
if (S_RESET_n_in = '0') then
sv_m_OUT <= "10000000000";
SV_c_out <= "00000000";
elsif (s_cLK_IN'eVENT and S_CLK_in = '1') then
if (CCALIBol01(4) = '1') then
SV_m_out(10 downto 3) <= CCALIBl001(7 downto 0);
end if;
if (CCALIBOL01(3) = '1') then
sv_M_OUT(2 downto 0) <= CCALIBl001(7 downto 5);
end if;
if (CCALIBOL01(5) = '1') then
sv_c_out(7 downto 0) <= CCALIBL001(7 downto 0);
end if;
end if;
end process;
CCALIBll11:
if (G_DEBUg = 1)
generate
process (s_clk_IN,S_RESet_n_in)
begin
if (S_reset_n_IN = '0') then
CCALIBLl01 <= '0';
elsif (s_clk_IN'evENT and S_CLK_in = '1') then
CCALIBll01 <= CCALIBlo01(4) and CCALIBlo01(3)
and CCALIBlo01(2)
and CCALIBLO01(1)
and CCALIBlo01(0);
end if;
end process;
s_adc_ch_ERROR_out <= CCALIBll01;
end generate CCALIBll11;
CCALIBIL11:
if (G_DEBug = 0)
generate
s_adC_CH_Error_out <= '0';
end generate CCALIBIL11;
end architecture behaVIORAL;