-- Copyright 2007 Actel Corporation. All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
-- Revision: 3.3
-- History:  Revision   Date                Author              Remarks.
library IEEe;
use IEee.Std_logic_1164.all;
use ieee.NUMERic_std.all;
entity compute_BLOCK is
generic (G_width_gaIN: INTEGEr := 11;
g_width_oFFSET: integer := 8;
G_Adc_bits_8_10_12: INTEGER := 0;
G_optimizatiON: Integer := 1;
G_sATURAte: integER := 1); port (s_clk_iN: in std_logiC;
s_rst_n_IN: in std_lOGIC;
s_busy_IN: in STD_LOgic;
S_datavalid_IN: in stD_LOGIC;
sv_adc_rESULT_in: in UNSIGNed(11 downto 0);
SV_GAIN_in: in unsigned(G_WIDth_gain-1 downto 0);
sv_off_SET_IN: in unsigned(G_width_ofFSET-1 downto 0);
s_busy_CALIB_Out: out std_LOGIC;
s_dATAVALID_calib_OUT: out std_logic;
SV_adc_resuLT_CALib_out: out UNSIGNED(11 downto 0));
end entity computE_BLOCK;

architecture behavioRAL of COMPUte_block is

component CCALIBo is
port (CCALIBL: in STD_logic_veCTOR(23 downto 0);
CCALIBI: in STd_logic_veCTOR(23 downto 0);
CCALIBol: out Std_logic_vECTOR(23 downto 0));
end component;

component CCALIBoi11 is
port (CCALIBl: in STD_logic_veCTOR(23 downto 0);
CCALIBI: in STD_logic_vecTOR(23 downto 0);
CCALIBol: out Std_logic_VECTOR(23 downto 0));
end component;

constant CCALIBli11: INTEGER := 1;

constant CCALIBII11: INTEGEr := 12;

constant CCALIBO011: INTEGER := CCALIBii11+g_width_gAIN;

constant CCALIBl011: INTEger := CCALIBo011-1;

constant CCALIBI011: inTEGER := CCALIBo011;

constant CCALIBo111: INTEGEr := CCALIBO011-3;

constant CCALIBL111: iNTEGER := CCALIBO011-1;

--- To Control Fanout in Synplify synthesis tool
attribute syn_maxfaN: INTEGER;

attribute SYN_maxfan of behAVIORAL: architecture is 1000;

type CCALIBi111 is (CCALIBooool,CCALIBLOOOl,CCALIBioool,CCALIBolool);

attribute CCALIBllooL: string;

attribute CCALIBllooL of CCALIBi111: type is "00 01 10 11";

signal CCALIBilooL: CCALIBi111;

signal CCALIBoiool: unsiGNED((CCALIBo011) downto 0);

signal CCALIBliool: unsignED((CCALIBo011) downto 0);

signal CCALIBiiool: STD_logic;

signal CCALIBO0OOL: UNSIGNed((CCALIBo011) downto 0);

signal CCALIBl0ool: unsigned(CCALIBII11-1 downto 0);

signal CCALIBI0OOL: UNSIGNED(CCALIBii11-1 downto 0);

signal CCALIBo1ool: std_LOGIC;

signal CCALIBl1ool: sTD_LOGIc_vector((CCALIBo011) downto 0);

signal CCALIBi1ooL: std_LOGIC;

begin
s_BUSY_Calib_out <= CCALIBi1oOL or s_busY_IN;
S_datavaliD_CALIB_out <= ((not (CCALIBi1ool or S_BUSY_in)) and s_datavALID_IN);
process (s_clk_IN,s_rsT_N_IN)
begin
if (S_RST_n_in = '0') then
sv_adc_RESULT_calib_OUT <= ( others => '0');
elsif (s_clK_IN'event and s_clk_in = '1') then
if (CCALIBiiool = '1') then
SV_ADc_result_CALIB_out <= CCALIBl0OOL;
end if;
end if;
end process;
CCALIBoolol:
if (G_adc_bits_8_10_12 = 0)
generate
process (S_clk_in,s_rST_N_IN)
variable CCALIBlolOL: UNSIGNed(3 downto 0);
begin
if (s_RST_N_in = '0') then
CCALIBOIOOL <= ( others => '0');
CCALIBLiool <= ( others => '0');
CCALIBO0OOL <= ( others => '0');
CCALIBLOLOL := "0000";
CCALIBI1OOL <= '0';
CCALIBiiool <= '0';
CCALIBiloOL <= CCALIBoooOL;
elsif (S_Clk_in'eveNT and s_CLK_IN = '1') then
case (CCALIBILOol) is
when CCALIBOOool =>
if (S_BUSY_in = '1') then
CCALIBI1OOL <= '1';
end if;
if (SV_OFF_set_in(7) = '0') then
CCALIBLIool <= ("0000"&SV_OFF_set_in&"00"&"0000000000");
else
CCALIBliooL <= ("1111"&SV_Off_set_in&"00"&"0000000000");
end if;
CCALIBo0OOL <= ( others => '0');
CCALIBloloL := ( others => '0');
CCALIBoiooL((CCALIBo011) downto CCALIBii11) <= "000000000000";
CCALIBOIOOl((CCALIBii11-1) downto 0) <= unSIGNED(sv_ADC_REsult_in((CCALIBii11-1) downto 0));
if (S_busy_in = '0') then
CCALIBILOOl <= CCALIBloool;
else
CCALIBilool <= CCALIBooOOL;
end if;
when CCALIBloool =>
if (unsignED(CCALIBlolol) < (G_width_gaiN)) then
CCALIBoiool <= UNSIGNEd(shift_leFT(unSIGNED(CCALIBOiool),
CCALIBlI11));
if (sv_gAIN_IN(TO_Integer(CCALIBLOLOl)) = '1') then
CCALIBO0OOL <= CCALIBOIOOl;
else
CCALIBo0ooL <= ( others => '0');
end if;
CCALIBliool <= UNSIgned(CCALIBl1ool);
CCALIBloloL := CCALIBlolol+1;
CCALIBILOol <= CCALIBLOOOL;
else
CCALIBlIOOL <= uNSIGNED(CCALIBl1OOL);
CCALIBiioOL <= '1';
CCALIBilool <= CCALIBioool;
end if;
when CCALIBioool =>
CCALIBi1oOL <= '0';
CCALIBIIOOL <= '0';
if (S_BUsy_in = '0') then
CCALIBilOOL <= CCALIBiOOOL;
else
CCALIBiLOOL <= CCALIBOoool;
end if;
when others =>
CCALIBilool <= CCALIBOOOOL;
end case;
end if;
end process;
CCALIBiolol:
if (G_saturate = 1)
generate
CCALIBo1ool <= '1' when sv_ADC_REsult_in(11 downto 0) = "111111111111" else
'0';
CCALIBi0ooL <= "111111111111" when ((CCALIBLIOOL(CCALIBl011)) or CCALIBo1oOL) = '1' else
(CCALIBliool((CCALIBo011)-2 downto (g_width_GAIN-1)));
end generate;
CCALIBOLLOL:
if (g_saturaTE = 0)
generate
CCALIBi0ool <= "111111111111" when (CCALIBliool(CCALIBL011)) = '1' else
(CCALIBliool((CCALIBo011)-2 downto (g_wIDTH_GAin-1)));
end generate;
CCALIBl0OOL <= "000000000000" when ((CCALIBliOOL(CCALIBi011))) = '1' else
CCALIBi0ool;
CCALIBllLOL:
if (g_optiMIZATIOn /= 0)
generate
CCALIBilloL: CCALIBo
port map (CCALIBl => STD_LOgic_vectOR(CCALIBliool),
CCALIBi => std_lOGIC_VEctor(CCALIBo0ool),
CCALIBol => CCALIBl1ool);
end generate;
CCALIBOilol:
if (not (g_optiMIZATIOn /= 0))
generate
CCALIBLILOl: CCALIBoi11
port map (CCALIBl => STD_logic_veCTOR(CCALIBliooL),
CCALIBi => std_logic_VECTOr(CCALIBo0ool),
CCALIBol => CCALIBL1ool);
end generate;
end generate;
CCALIBIILOL:
if (G_ADC_Bits_8_10_12 = 1)
generate
process (s_CLK_IN,S_RST_N_in)
variable CCALIBlOLOL: unsiGNED(3 downto 0);
begin
if (s_rst_N_IN = '0') then
CCALIBoiool <= ( others => '0');
CCALIBliool <= ( others => '0');
CCALIBo0ool <= ( others => '0');
CCALIBlolol := "0000";
CCALIBI1OOL <= '0';
CCALIBiiool <= '0';
CCALIBilOOL <= CCALIBooooL;
elsif (s_clk_in'Event and s_CLK_IN = '1') then
case (CCALIBilool) is
when CCALIBOOOOL =>
if (s_BUSY_In = '1') then
CCALIBI1OOl <= '1';
end if;
if (SV_off_set_IN(7) = '0') then
CCALIBliool <= ("000000"&SV_off_set_iN&"0000000000");
else
CCALIBLIOOL <= ("111111"&sv_off_sET_IN&"0000000000");
end if;
CCALIBo0ool <= ( others => '0');
CCALIBlolol := ( others => '0');
CCALIBOIOOL((CCALIBo011) downto CCALIBii11) <= "000000000000";
CCALIBoioOL((CCALIBii11-1) downto (CCALIBii11-2)) <= "00";
CCALIBoiool((CCALIBII11-3) downto 0) <= UNSIGNED(SV_ADC_result_in((CCALIBIi11-1) downto 2));
if (S_BUsy_in = '0') then
CCALIBilool <= CCALIBloool;
else
CCALIBilool <= CCALIBooool;
end if;
when CCALIBLOool =>
if (unsigned(CCALIBLOLOl) < (g_wiDTH_GAIn)) then
CCALIBoiool <= UNSIgned(shift_leFT(unsignED(CCALIBoiooL),
CCALIBli11));
if (sv_gAIN_IN(to_integeR(CCALIBlolol)) = '1') then
CCALIBo0ooL <= CCALIBoiooL;
else
CCALIBO0OOL <= ( others => '0');
end if;
CCALIBLIOOL <= unsigned(CCALIBl1oOL);
CCALIBlolol := CCALIBlolol+1;
CCALIBILOOl <= CCALIBLOOol;
else
CCALIBliool <= unsIGNED(CCALIBl1ool);
CCALIBiiool <= '1';
CCALIBilool <= CCALIBioooL;
end if;
when CCALIBIOOOL =>
CCALIBi1ool <= '0';
CCALIBIIOol <= '0';
if (S_BUSY_in = '0') then
CCALIBilooL <= CCALIBioool;
else
CCALIBilool <= CCALIBooooL;
end if;
when others =>
CCALIBilooL <= CCALIBOOOOL;
end case;
end if;
end process;
CCALIBiolol:
if (G_saturate = 1)
generate
CCALIBO1ool <= '1' when SV_adc_resulT_IN(11 downto 2) = "1111111111" else
'0';
CCALIBI0OOl <= "111111111111" when ((CCALIBLIOol(CCALIBO111)) or CCALIBo1OOL) = '1' else
(CCALIBLIOOL((g_width_GAIN+8) downto (g_width_gAIN-1))&"00");
end generate;
CCALIBollOL:
if (g_SATURAte = 0)
generate
CCALIBI0OOL <= "111111111111" when (CCALIBlIOOL(CCALIBo111)) = '1' else
(CCALIBLIOOL((G_WIdth_gain+8) downto (G_WIDTh_gain-1))&"00");
end generate;
CCALIBl0ooL <= "000000000000" when ((CCALIBliooL(CCALIBl111))) = '1' else
CCALIBI0ool;
CCALIBO0lol:
if (g_oPTIMIZAtion /= 0)
generate
CCALIBIllol: CCALIBo
port map (CCALIBl => std_lOGIC_VEctor(CCALIBLiool),
CCALIBi => sTD_LOGIc_vector(CCALIBO0OOL),
CCALIBOL => CCALIBl1ool);
end generate;
CCALIBL0lol:
if (not (G_OPTimization /= 0))
generate
CCALIBlilol: CCALIBoi11
port map (CCALIBl => STD_LOgic_vectOR(CCALIBliool),
CCALIBi => std_LOGIC_Vector(CCALIBo0OOL),
CCALIBol => CCALIBl1ool);
end generate;
end generate;
CCALIBI0LOL:
if (g_adc_bITS_8_10_12 = 2)
generate
process (s_clk_in,S_Rst_n_in)
variable CCALIBLOLOL: uNSIGNED(3 downto 0);
begin
if (s_rst_N_IN = '0') then
CCALIBoioOL <= ( others => '0');
CCALIBLIOOL <= ( others => '0');
CCALIBo0ool <= ( others => '0');
CCALIBlOLOL := "0000";
CCALIBI1ool <= '0';
CCALIBiiool <= '0';
CCALIBiloOL <= CCALIBooooL;
elsif (S_clk_in'evENT and s_CLK_IN = '1') then
case (CCALIBILOOL) is
when CCALIBoooOL =>
if (s_busy_in = '1') then
CCALIBI1ool <= '1';
end if;
if (sv_oFF_SET_in(7) = '0') then
CCALIBliool <= ("000000"&SV_off_set_IN&"0000000000");
else
CCALIBlIOOL <= ("111111"&SV_OFf_set_in&"0000000000");
end if;
CCALIBo0OOL <= ( others => '0');
CCALIBloloL := ( others => '0');
CCALIBoiool((CCALIBo011) downto CCALIBii11) <= "000000000000";
CCALIBoioOL((CCALIBII11-1) downto (CCALIBii11-2)) <= "00";
CCALIBoIOOL((CCALIBii11-3) downto 0) <= unsigned(sv_adc_reSULT_In((CCALIBii11-1) downto 2));
if (S_BUSY_in = '0') then
CCALIBilool <= CCALIBloooL;
else
CCALIBilool <= CCALIBOOOOL;
end if;
when CCALIBloool =>
if (Unsigned(CCALIBloloL) < (g_width_GAIN)) then
CCALIBoiool <= UNSIGNEd(SHIFt_left(unsigned(CCALIBoiool),
CCALIBLi11));
if (sv_gaIN_IN(TO_INteger(CCALIBlolol)) = '1') then
CCALIBo0oOL <= CCALIBoiool;
else
CCALIBo0oOL <= ( others => '0');
end if;
CCALIBliool <= UNSIgned(CCALIBl1ool);
CCALIBlolOL := CCALIBlolol+1;
CCALIBILOOL <= CCALIBLOOol;
else
CCALIBLiool <= unsigned(CCALIBl1ooL);
CCALIBiiool <= '1';
CCALIBILOol <= CCALIBiooOL;
end if;
when CCALIBIOool =>
CCALIBi1ool <= '0';
CCALIBIIool <= '0';
if (s_busy_in = '0') then
CCALIBilool <= CCALIBioool;
else
CCALIBILOOL <= CCALIBooOOL;
end if;
when others =>
CCALIBilool <= CCALIBOOOOL;
end case;
end if;
end process;
CCALIBioloL:
if (g_saTURATE = 1)
generate
CCALIBo1OOL <= '1' when Sv_adc_resULT_IN(11 downto 4) = "11111111" else
'0';
CCALIBi0ool <= "111111111111" when ((CCALIBliool(CCALIBo111)) or CCALIBo1ool) = '1' else
(CCALIBliool((g_width_GAIN+8) downto (g_width_gaIN+1))&"0000");
end generate;
CCALIBolloL:
if (g_SATURATE = 0)
generate
CCALIBi0OOL <= "111111111111" when (CCALIBlioOL(CCALIBO111)) = '1' else
(CCALIBliool((G_WIDth_gain+8) downto (g_wIDTH_GAin+1))&"0000");
end generate;
CCALIBl0ooL <= "000000000000" when ((CCALIBliooL(CCALIBl111))) = '1' else
CCALIBi0ooL;
CCALIBo1loL:
if (G_optimizatiON /= 0)
generate
CCALIBilLOL: CCALIBo
port map (CCALIBl => std_LOGIC_vector(CCALIBlIOOL),
CCALIBi => std_LOGIC_vector(CCALIBO0Ool),
CCALIBol => CCALIBL1OOl);
end generate;
CCALIBl1loL:
if (not (g_OPTIMIZAtion /= 0))
generate
CCALIBlilol: CCALIBoi11
port map (CCALIBl => STD_LOGic_vectoR(CCALIBliooL),
CCALIBi => std_logIC_VECtor(CCALIBO0OOL),
CCALIBOL => CCALIBl1oOL);
end generate;
end generate;
end architecture BEHAVIORal;