-------------------------------------------------------------------------------
-- (c) Copyright 2006 Actel Corporation
--
-- name:		assc.vhd
-- function:	ADC Sample Sequence Controller (ASSC) block
-- Rev:			1.2 28Apr06
--
-------------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
fmvgpwbdcxs is generic(knrjvwspqzm:integer range 2 to 6:=6;ddqwgtngbxc:integer
range 0 to 63:=0;whxdkdmhjwj:integer range 0 to 9:=0;cpcqjrjtppx:integer range
0 to 1:=1;pqqkvvvcbmx:integer range 0 to 1:=0;mqbcdwzwhzc:integer range 0 to
1:=0;pxzwzhfwkqm:integer range 0 to 15:=0;dgsjdxsjscf:integer range 0 to 1:=0;
rcbvmqmwnjn:integer range 0 to 1:=0;vhxpkfzhvxk:integer range 0 to 255:=0;
kksfgnxtcxn:integer range 0 to 1:=0;dggdcrrffcs:integer range 0 to 255:=0;
jphnsqvgftr:integer range 0 to 1023:=0;csnxdprbsgk:integer range 0 to 2047:=0);
port(cgxfkzgfxxt:in std_logic;sbhnwnnqqnk:in std_logic;zqvgfpnsxsg:in std_logic;
wdcnjkkrrsk:in std_logic;znmksvkhcrj:in std_logic;xhtjdbqjhrg:in std_logic;
gwjkmcbfwch:in std_logic_vector(8 downto 0);vkdhvmkrswc:in std_logic;
gzmzdjpwcfc:in std_logic_vector(8 downto 0);cfxfrwgjccr:in std_logic;
vhqjcrxqhqk:in std_logic_vector(8 downto 0);vhsprbpmpnr:in std_logic;
bsxspqmnrmb:out std_logic;vcwfnxxvfqr:in std_logic_vector(8 downto 0);
vmfrcqmdjgd:in std_logic;ksbhwjctscp:out std_logic_vector(8 downto 0);
jngpzgpmcms:out std_logic;hbxwhvjzqbt:out std_logic;wpbjqxfvzwx:out
std_logic_vector(8 downto 0);mkzhxpjcvvm:out std_logic_vector(8 downto 0);
nptwvwnctcg:out std_logic;ddvbdtxtbpx:out std_logic;mksbfqnmmgw:out
std_logic_vector(8 downto 0);nqjzptmmzdw:in std_logic_vector(8 downto 0);
grkzscwpbcr:out std_logic;jdnjkrhcwrh:in std_logic;zkskcqkrfsp:in std_logic;
mwnmtbczdwq:in std_logic;njqxjcrhvhw:in std_logic_vector(knrjvwspqzm-1 downto 0)
;vtfmnngzbjn:out std_logic_vector(knrjvwspqzm-1 downto 0);cmbpphsszmt:out
std_logic;pmszxrxmrnd:out std_logic;zkvtchzdcbq:out std_logic;mgddcvfjsnm:out
std_logic;drfvdfjpksm:out std_logic;cwtcnjnqgct:out std_logic;fjbdwbzdmfq:in
std_logic;ngvxdqfqsgb:in std_logic;dpbnwjjwpvs:in std_logic_vector(11 downto 0);
gpvwdfsrrwc:out std_logic;mcvhqmpzqjh:out std_logic;bpngcgrgmxx:out std_logic;
zjbjphzzgfc:out std_logic_vector(3 downto 0);pbzhdbbgwjr:out std_logic;
fqdhqfwnwmf:out std_logic_vector(4 downto 0);hgxfbxjfkvd:out std_logic_vector(7
downto 0);rqbqkfndrgv:out std_logic_vector(7 downto 0);xmknnnzsbsb:out
std_logic_vector(9 downto 0);gjgxnxqkbht:out std_logic_vector(10 downto 0));end
fmvgpwbdcxs;architecture twzmfpzvmcf of fmvgpwbdcxs is constant
hnvgngcgxqv:std_logic_vector(2 downto 0):="000";constant
nqsmzqnjmrw:std_logic_vector(2 downto 0):="001";constant
zzkwmmdbxsp:std_logic_vector(2 downto 0):="010";constant
rrkzczwdwsc:std_logic_vector(2 downto 0):="011";constant
hjsnsxjgcdh:std_logic_vector(2 downto 0):="100";constant
vxcfjzvsvhk:std_logic_vector(2 downto 0):="101";constant
tmqfdmdqjts:std_logic_vector(2 downto 0):="110";constant
rdqqcddkdwq:std_logic_vector(2 downto 0):="111";constant
bjsvghjhbmx:std_logic_vector(2 downto 0):="001";constant
chgvmjshrrw:std_logic_vector(2 downto 0):="010";constant
bmhfcgnbbxr:std_logic_vector(2 downto 0):="011";constant
gdgczndxskv:std_logic_vector(2 downto 0):="100";constant
kzqsqsbqhrw:std_logic_vector(2 downto 0):="101";constant
wnxmqrmxxnh:std_logic_vector(2 downto 0):="110";constant
hbsskxtsqbt:std_logic_vector(5 downto 0):="000000";constant
tpbpbbzppsz:std_logic_vector(7 downto 0):="11111111";signal
xdtnvttdgcs:std_logic;signal bztdcfmmchj:std_logic;signal
zhdqczdhtzp:std_logic_vector(8 downto 0);signal fqnwxsdcmsb:std_logic;signal
ptptntwwvwd:std_logic_vector(8 downto 0);signal skcmqsgbhfk:std_logic;signal
gqsjsrbgvjp:std_logic_vector(8 downto 0);signal srwbwxtkzcq:std_logic;signal
jmrkjgnrnps:std_logic;signal hsxdqshqjjj:std_logic_vector(8 downto 0);signal
cfhqhmczswz:std_logic;signal dcxfgfftfpf:std_logic_vector(8 downto 0);signal
mdbqczqzcfh:std_logic;signal kftxkzdmgnn:std_logic;signal
zrpgtngkxsf:std_logic_vector(8 downto 0);signal vcvfbbmqhkz:std_logic_vector(8
downto 0);signal cndpcdhdzdz:std_logic;signal qxvnwqhdfph:std_logic;signal
qjvbvnnqdnc:std_logic_vector(8 downto 0);signal vcqgtdbzfmz:std_logic_vector(8
downto 0);signal zcccnjctmpr:std_logic;signal srjknzgkqcx:std_logic;signal
vksvspxxfbc:std_logic;signal zwccvxxrdvf:std_logic;signal
qgfkksmdtqm:std_logic_vector(knrjvwspqzm-1 downto 0);signal
jpfggbzcssz:std_logic_vector(knrjvwspqzm-1 downto 0);signal
vswcgkhjqbg:std_logic;signal xpjccbwgqkw:std_logic;signal tbnnndsxsdh:std_logic;
signal ggqzqbfxcmh:std_logic;signal btgwwsmjstm:std_logic;signal
knpqbcffchx:std_logic;signal jjqhbgsgzmt:std_logic;signal
pqcwcxxjxzr:std_logic_vector(11 downto 0);signal tkrjwcffspp:std_logic;signal
fgjjfdkjggf:std_logic;signal dhjxqvknpjm:std_logic;signal
rrctqpbbmtj:std_logic_vector(3 downto 0);signal mwgjcmtxrrd:std_logic;signal
xdcczgmbftx:std_logic_vector(4 downto 0);signal mqgdsrhchqq:std_logic_vector(7
downto 0);signal xtjphwvtmmb:std_logic_vector(7 downto 0);signal
jjwthdwfwkm:std_logic_vector(9 downto 0);signal nksfrfkcttc:std_logic_vector(10
downto 0);type hnjbjrqsbmg is(mdqdmchqsjk,zjjmzcsxggj,nvnpbtnnhwb,zgqrpqvjtwm,
rvsskdxmcct,ptgdvkqmfxz,rcgmzbqbdhp,xdbhgfkhtkv,bjrtpbmfdvt,jvfmnrmnrsc,
gmccksdwzbb,pdtbxbcjmqv,frtsmvmjzjs,dnkbdnxmrsb,dtdsjrnddkb,jqktphcjtcx);signal
jzzdfrmzwdj:hnjbjrqsbmg;signal cmsjqxtsvdj:hnjbjrqsbmg;signal
wvjbzknkjft:std_logic;signal wwhrbsjdjpn:std_logic;signal wkpfnwqwgcb:std_logic;
signal bksczsjcvgb:std_logic;signal jkdrssrksxm:std_logic;signal
jdhgstfqkjm:std_logic;signal znbkwkbspdc:std_logic;signal fsrxhtjthgw:std_logic;
signal tchdhxxwqng:std_logic;signal dtcvhtqxgdc:std_logic;signal
ghpdprpcqzt:std_logic;signal nssvdqpkknt:std_logic;signal
bnrsdrtmtsg:std_logic_vector(knrjvwspqzm-1 downto 0);signal
bksnhfwfshc:std_logic;signal jhkbkqjtkbs:std_logic;signal ktwrhqstzjg:std_logic;
signal kzkrfjncknf:std_logic_vector(2 downto 0);signal gzsjwmsktkv:unsigned(6
downto 0);signal ztmbcbbpsvx:std_logic;signal xnrcgsmbqbc:std_logic;signal
xcppwrfzcts:std_logic;signal tcmhkgtbwjv:std_logic;signal znbmnfdbzvr:std_logic;
signal nsqndpvcghw:std_logic_vector(2 downto 0);signal bfcqztswjqb:std_logic;
signal jvxdjfpfpjw:std_logic_vector(4 downto 0);signal
dspfgfmqhwh:std_logic_vector(4 downto 0);signal dmjnzckwkmc:std_logic;signal
nbhxrgznwqt:std_logic_vector(7 downto 0);signal ptxbvztnpnf:std_logic_vector(7
downto 0);signal dppmsqczgtw:std_logic;signal nsbfthprvtx:std_logic;signal
cbcscwbfmnc:std_logic_vector(8 downto 0);signal svpqbbcnvqz:std_logic_vector(2
downto 0);signal nsqzfjtdhmd:std_logic_vector(knrjvwspqzm-1 downto 0);signal
dvmxrnjphfr:std_logic;signal hgqdwrxvgzm:std_logic_vector(knrjvwspqzm-1 downto
0);signal vwdjdwrxnwz:std_logic;signal zgzrtwwghwq:std_logic;signal
svqfpjhxrvg:std_logic;signal bxdwskbrngz:std_logic;signal
jwnfnggjkmn:std_logic_vector(3 downto 0);signal pfkhhxxsrzp:std_logic_vector(3
downto 0);signal qjswdxfpzkp:std_logic;signal zdrphkhqvrh:std_logic;signal
wzdwjdgptwq:std_logic_vector(7 downto 0);signal dbcvwwhvvwh:std_logic_vector(7
downto 0);signal cjhmcbjwdht:std_logic;signal trnwxjxxrbp:std_logic_vector(
knrjvwspqzm-1 downto 0);signal xhfzbcfrwqc:std_logic;signal
ssssgmdwsms:std_logic;signal sgbwkmbvtjw:std_logic;signal xjtzrtrmmhp:std_logic;
signal kqdhxmzqqxh:std_logic;signal rxrvgqbkqxp:std_logic;signal
gsvgdsdxdrb:std_logic;signal bmzgvdtnsmc:std_logic;signal vzqjrhpgqjj:std_logic;
signal fkxcbccrpzt:std_logic;signal nthjkdpsqfq:std_logic_vector(11 downto 0);
signal kgcjjcqbnqb:std_logic;signal gtdnggtvcgr:std_logic;signal
kzdxfwqwvrt:std_logic;signal zbhmfptrcmn:std_logic;signal gtxqsppgcmn:std_logic;
signal crgqqkcrfvm:std_logic;signal jzwhhbvmkpk:std_logic;signal
njsdcspkqtt:std_logic;signal bcmkdjqtngz:std_logic;signal hmskprmkfbx:std_logic;
signal hdxtpkktfvz:std_logic;signal qvkpfznsfjx:std_logic;signal
dffjbswcksf:std_logic_vector(9 downto 0);signal sxqvnxkkjsh:std_logic_vector(9
downto 0);signal xtghwvhzbdc:std_logic_vector(10 downto 0);signal
bwngcbddzsh:std_logic_vector(10 downto 0);signal vjxvhntknbb:std_logic;signal
dcgsmprnhgv:std_logic;signal pbvbrcqzprf:std_logic;signal qswrjqvjvnw:std_logic;
signal rjwrrthmpnh:std_logic;signal mzpwxrnkzkh:std_logic;signal
hvxbrhbkcfk:std_logic;signal bdbpcvshhqt:std_logic;signal cqxzbmfvwmz:std_logic;
signal cgksdcqxqds:std_logic;begin nsqndpvcghw<=vcqgtdbzfmz(8 downto 6);
jvxdjfpfpjw<=vcqgtdbzfmz(4 downto 0);nbhxrgznwqt<=vcqgtdbzfmz(7 downto 0);
kzkrfjncknf<=vcqgtdbzfmz(2 downto 0);jwnfnggjkmn<=vcqgtdbzfmz(8 downto 5);
wzdwjdgptwq<=vcqgtdbzfmz(7 downto 0);nsqzfjtdhmd<=vcqgtdbzfmz(knrjvwspqzm-1
downto 0);process(xdtnvttdgcs,bztdcfmmchj)begin if bztdcfmmchj='0' then
bksczsjcvgb<='0';wwhrbsjdjpn<='0';wkpfnwqwgcb<='0';jdhgstfqkjm<='1';elsif
rising_edge(xdtnvttdgcs)then wwhrbsjdjpn<=knpqbcffchx;wkpfnwqwgcb<=wwhrbsjdjpn;
jdhgstfqkjm<=wvjbzknkjft and jkdrssrksxm;if wvjbzknkjft='1' and jkdrssrksxm='1'
then bksczsjcvgb<='0';elsif wkpfnwqwgcb='1' and wwhrbsjdjpn='0' then
bksczsjcvgb<='1';end if;end if;end process;process(xdtnvttdgcs,bztdcfmmchj)
begin if bztdcfmmchj='0' then znbkwkbspdc<='0';elsif rising_edge(xdtnvttdgcs)
then if fsrxhtjthgw='1' or skcmqsgbhfk='0' then znbkwkbspdc<='0';elsif
zwccvxxrdvf='1' then znbkwkbspdc<='1';end if;end if;end process;
fsrxhtjthgw<=znbkwkbspdc and wvjbzknkjft and tchdhxxwqng;process(xdtnvttdgcs,
bztdcfmmchj)begin if bztdcfmmchj='0' then trnwxjxxrbp<=(others=>'0');elsif
rising_edge(xdtnvttdgcs)then if zwccvxxrdvf='1' and znbkwkbspdc='0' then
trnwxjxxrbp<=qgfkksmdtqm;end if;end if;end process;process(xdtnvttdgcs,
bztdcfmmchj)begin if bztdcfmmchj='0' then dtcvhtqxgdc<='0';elsif rising_edge(
xdtnvttdgcs)then if fsrxhtjthgw='1' or skcmqsgbhfk='0' then dtcvhtqxgdc<='0';
elsif ghpdprpcqzt='1' then dtcvhtqxgdc<='1';end if;end if;end process;
jhkbkqjtkbs<=wvjbzknkjft and bksnhfwfshc;ktwrhqstzjg<=jhkbkqjtkbs and
znbmnfdbzvr;process(xdtnvttdgcs,bztdcfmmchj)begin if bztdcfmmchj='0' then