-- Copyright 2007 Actel Corporation. All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN                              
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED                              
-- IN ADVANCE IN WRITING.                                                                        
-- Revision: 2.2                                                                                 
--   Revision   Date        Author   Remarks                                                     
-- SVN Revision Information:
-- SVN $Revision: $                                   
library iEee;
use IEEE.STD_LOgic_1164.all;
use ieee.numeric_STD.all;
entity calibIP is
generic (g_DEBUG: integer := 0;
g_use_srAM_TILEs: INTEGER := 0;
G_WIDTh_gain: INTEGEr := 11;
g_width_OFFSET: integER := 8;
G_adc_bits_8_10_12: INTEGER := 0;
g_OPTIMIzation: INTEGER := 0;
g_saturate: iNTEGER := 1); port (clk: in STD_logic;
reset_n: in STD_LOGIc;
iniT_CLK: in std_LOGIC;
Init_data: in STD_logic_veCTOR(8 downto 0);
Init_addr: in STD_LOGic_vectoR(10 downto 0);
init_rom_wEN: in STD_LOGic;
INit_coeff_WEN: in std_loGIC;
inIT_DONE: in std_lOGIC;
ADC_CH_error: out std_LOGIC;
bUSY_CALIb: out std_lOGIC;
DATAVALId_calib: out STD_logic;
aDC_RESUlt_calib: out std_lOGIC_VEctor(11 downto 0);
adc_START: in std_logic;
CH_NUmber: in std_logIC_VECtor(4 downto 0);
busy: in sTD_LOGIc;
DATAValid: in STD_logic;
adc_RESULT: in std_logIC_VECTor(11 downto 0));
end entity caLIBIP;

architecture BEHAVIOral of CALIBIP is

component CALIBIP_clram is
generic (g_deBUG: INTEger := 0;
G_use_sram_TILES: integeR := 0);
port (s_clk_iN: in STD_LOgic;
s_resET_N_IN: in std_LOGIC;
s_init_CLK_IN: in std_loGIC;
SV_init_data_IN: in std_lOGIC_VEctor(8 downto 0);
sv_init_ADDR_In: in STD_LOGIc_vector(10 downto 0);
S_INIt_rom_wen_IN: in std_logic;
S_INIT_coeff_weN_IN: in STd_logic;
s_init_doNE_IN: in STD_LOGic;
s_adc_ch_eRROR_Out: out Std_logic;
S_adc_start_IN: in std_lOGIC;
SV_CH_number_iN: in STD_logic_vecTOR(4 downto 0);
sv_M_OUT: out std_logIC_VECtor(10 downto 0);
sv_C_OUT: out std_logic_VECTOr(7 downto 0));
end component;

component COMPUTE_block is
generic (g_wiDTH_GAIn: intEGER := 11;
G_Width_offsET: integer := 8;
G_ADC_bits_8_10_12: INTEGER := 1;
G_optimizaTION: integer := 0;
G_SAturate: iNTEGER := 1);
port (s_clk_in: in std_lOGIC;
s_rst_n_iN: in std_lOGIC;
s_buSY_IN: in STD_LOGIc;
S_datavaliD_IN: in STD_LOgic;
sv_adc_RESULT_in: in unsIGNED(11 downto 0);
SV_gain_in: in Unsigned(G_WIDth_gain-1 downto 0);
sv_off_set_IN: in Unsigned(G_width_ofFSET-1 downto 0);
S_busy_calIB_OUT: out std_LOGIC;
s_datavalID_CALib_out: out STD_logic;
SV_adc_resulT_CALIb_out: out Unsigned(11 downto 0));
end component;

attribute SYN_Maxfan: intEGER;

attribute SYN_maxfan of behaviORAL: architecture is 1000;

signal sv_M: sTD_LOGIC_vector(10 downto 0);

signal sv_c: STD_logic_veCTOR(7 downto 0);

signal S_clk_in: STD_LOGic;

signal S_Reset_n_in: STD_logic;

signal s_INIT_CLk_in: stD_LOGIC;

signal sv_iNIT_DATa_in: STD_Logic_vectOR(8 downto 0);

signal Sv_init_adDR_IN: std_LOGIC_vector(10 downto 0);

signal S_INIT_rom_wen_IN: std_logIC;

signal S_INit_coeff_WEN_IN: std_LOGIC;

signal s_iNIT_DONe_in: std_logIC;

signal s_ADC_CH_error_oUT: STD_logic;

signal S_busy_caliB_OUT: STD_logic;

signal s_dATAVALID_calib_OUT: Std_logic;

signal sv_adc_rESULT_Calib_oUT: unsigNED(11 downto 0);

signal s_adc_START_in: std_logic;

signal sv_ch_NUMBER_in: STd_logic_vECTOR(4 downto 0);

signal s_busy_in: std_logic;

signal S_DATAValid_in: std_logic;

signal sv_adc_RESULT_in: Unsigned(11 downto 0);

begin
s_clk_IN <= CLK;
S_reset_n_IN <= RESEt_n;
s_init_cLK_IN <= init_clk;
SV_INIt_data_iN <= INit_data;
SV_INIT_addr_in <= INIT_addr;
S_INIT_rom_wen_IN <= init_rom_WEN;
s_INIT_COeff_wen_IN <= inIT_COEFf_wen;
s_inIT_DONE_in <= init_DONE;
ADC_ch_error <= S_adc_ch_eRROR_Out;
busy_calIB <= s_busy_cALIB_OUt;
daTAVALID_calib <= s_DATAVALid_calib_OUT;
adc_result_CALIB <= STD_logic_veCTOR(SV_ADC_result_cALIB_out);
S_ADC_Start_in <= ADC_STArt;
sv_ch_nuMBER_IN <= CH_number;
s_BUSY_IN <= busy;
S_DATavalid_iN <= datavaliD;
sv_adc_reSULT_In <= Unsigned(adc_resULT);
u_clraM: CALibip_clraM
generic map (G_debug => G_debug,
g_use_srAM_TILes => G_Use_sram_tILES)
port map (S_CLK_In => s_clk_in,
S_RESEt_n_in => S_REset_n_in,
s_init_CLK_IN => s_iNIT_CLK_in,
sv_init_daTA_IN => SV_INit_data_iN,
SV_Init_addr_IN => sv_INIT_ADdr_in,
S_INIT_rom_wen_IN => S_INIT_rom_wen_IN,
s_init_coEFF_WEN_in => s_INIT_COeff_wen_IN,
S_INIT_done_in => S_INIt_done_in,
s_ADC_CH_error_oUT => S_ADC_ch_error_OUT,
S_ADc_start_IN => S_Adc_start_IN,
sv_ch_NUMBER_in => sv_ch_NUMBER_in,
sv_m_OUT => SV_M,
SV_C_Out => sv_c);
u_comPUTE: cOMPUTE_Block
generic map (G_WIDTH_gain => g_widTH_GAIN,
G_WIdth_offsET => G_WIdth_offseT,
g_ADC_BITs_8_10_12 => g_ADC_BIts_8_10_12,
g_optIMIZATIon => g_optimizATION,
G_saturate => G_SATUrate)
port map (Sv_adc_resULT_IN => SV_ADc_result_IN,
SV_gain_in => unsigned(sv_m),
sv_ofF_SET_in => UNSIGned(SV_C),
s_clk_in => S_Clk_in,
S_RST_N_in => s_reset_n_IN,
S_Busy_in => S_BUsy_in,
s_DATAVAlid_in => s_dataVALID_in,
S_BUSy_calib_oUT => S_busy_calIB_OUT,
S_DAtavalid_CALIB_out => s_datavaliD_CALIb_out,
SV_Adc_result_CALIB_out => SV_ADC_result_caLIB_Out);
end architecture BEHAvioral;