--      Version:  3.0
--         Date:  May 5th, 2008
--  Description:  Top level module
-- SVN Revision Information:
-- SVN $Revision: 346 $
-- SVN $Date: 2008-01-16 07:57:25 -0800 (Wed, 16 Jan 2008) $  
-- COPYRIGHT 2008 BY ACTEL 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM ACTEL CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- ACTEL FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
library Ieee;
use ieee.sTD_logic_1164.all;
use IEEE.sTD_LOGIC_unsigned.all;
use ieee.numeric_stD.all;
entity CORepwm is
generic (FAMIly: INTeger := 0;
PWM_NUm: INTEGER := 1;
APB_dwidth: INTeger := 8;
fixed_prESCALE_En: integeR := 1;
Fixed_prescaLE: inteGER := 8;
fixed_peRIOD_EN: INteger := 0;
fixeD_PERIOD: INTEGer := 8;
Dac_mode1: INTeger := 0;
DAC_Mode2: INTEGEr := 0;
DAC_mode3: INTeger := 0;
dac_MODE4: inTEGER := 0;
DAC_Mode5: INTEGER := 0;
dac_MODE6: inteGER := 0;
Dac_mode7: INTEGEr := 0;
DAc_mode8: INTEGER := 0;
DAc_mode9: INTEGER := 0;
DAc_mode10: iNTEGER := 0;
dac_mode11: INTEGEr := 0;
dAC_MODE12: integer := 0;
DAC_Mode13: Integer := 0;
dac_modE14: INTEGEr := 0;
dac_mode15: iNTEGER := 0;
DAC_MOde16: integer := 0;
SHADow_reg_en1: inteGER := 0;
SHADOW_reg_en2: integeR := 0;
SHADOW_Reg_en3: integer := 0;
shadow_rEG_EN4: INTeger := 0;
SHAdow_reg_en5: integeR := 0;
shadow_reG_EN6: INTEGer := 0;
SHADOW_reg_en7: INTeger := 0;
SHADOW_reg_en8: Integer := 0;
SHAdow_reg_en9: integer := 0;
shadow_rEG_EN10: INTEGER := 0;
SHADOw_reg_en11: INteger := 0;
shadow_REG_EN12: INTEGER := 0;
shaDOW_REG_en13: INTEGER := 0;
shadow_reG_EN14: integer := 0;
shadow_reg_EN15: integer := 0;
sHADOW_REg_en16: INTEGER := 0;
fIXED_PWm_pos_en1: INTEGer := 1;
fixed_pwM_POS_EN2: intEGER := 1;
Fixed_pwm_POS_EN3: integer := 1;
FIXED_pwm_pos_eN4: INTeger := 1;
fixed_pWM_POS_en5: integer := 1;
FIXEd_pwm_pos_eN6: INTEGer := 1;
fixed_PWM_POS_en7: integer := 1;
FIXed_pwm_pos_EN8: INTEGEr := 1;
FIXEd_pwm_pos_eN9: INTEGEr := 1;
fixed_pwm_POS_EN10: INteger := 1;
FIxed_pwm_poS_EN11: Integer := 1;
FIXED_pwm_poS_EN12: INTeger := 1;
FIXed_pwm_POS_EN13: inTEGER := 1;
fiXED_Pwm_pos_EN14: INteger := 1;
fixed_pWM_POs_en15: integeR := 1;
FIXED_pwm_pOS_EN16: iNTEGEr := 1;
fiXED_Pwm_poseDGE1: Integer := 0;
fiXED_Pwm_poseDGE2: integER := 0;
fixeD_PWM_posedGE3: INTeger := 0;
FIXed_pwm_POSEDGe4: INTEGer := 0;
fixeD_PWM_posedGE5: INTEGer := 0;
Fixed_pwM_POSedge6: integeR := 0;
fixeD_PWM_posedgE7: integeR := 0;
fIXED_pwm_posEDGE8: iNTEGEr := 0;
fiXED_Pwm_posEDGE9: iNTEGER := 0;
fIXED_pwm_poSEDGE10: INTEger := 0;
FIXED_pwm_poSEDGE11: intEGER := 0;
Fixed_PWM_Posedge12: INTEGEr := 0;
fixed_PWM_Posedge13: INTEger := 0;
fixeD_PWM_posedgE14: INTEGEr := 0;
fixED_PWm_posedGE15: Integer := 0;
fixeD_PWM_posedGE16: Integer := 0;
fixed_PWM_Neg_en1: integer := 0;
fixeD_PWM_neg_eN2: intEGER := 0;
FIXEd_pwm_nEG_EN3: intEGER := 0;
fixed_PWM_Neg_en4: INTEGer := 0;
FIxed_pwm_NEG_en5: inTEGER := 0;
fixed_PWM_neg_en6: inTEGER := 0;
fixeD_PWM_neg_en7: integER := 0;
fIXEd_pwm_neg_eN8: inteGER := 0;
fixed_PWM_NEG_en9: INTEGER := 0;
fixed_pwm_NEG_EN10: integER := 0;
FIXED_Pwm_neg_en11: INTEger := 0;
fIXED_PWm_neg_en12: INTEGER := 0;
fixed_PWM_NEG_en13: inteGER := 0;
Fixed_pwm_nEG_EN14: integer := 0;
fIXED_PWM_neg_en15: iNTEGER := 0;
FIXED_Pwm_neg_en16: INTEGER := 0;
Fixed_pwm_neGEDGE1: INTEGEr := 0;
FIXED_pwm_negedgE2: INTEGER := 0;
fixed_pwm_NEGEDGe3: INTeger := 0;
FIXED_Pwm_negedge4: inteGER := 0;
FIXED_PWm_negedge5: integer := 0;
fixed_pwM_NEGEDGe6: INTEGer := 0;
fIXED_PWM_negedge7: integer := 0;
Fixed_pwm_nEGEDGE8: iNTEGER := 0;
fixed_PWM_NEGedge9: INteger := 0;
Fixed_pwm_nEGEDGE10: iNTEGER := 0;
fixed_pwm_NEGEDGe11: INTEGER := 0;
Fixed_pwm_neGEDGE12: integeR := 0;
Fixed_pwm_neGEDGE13: integeR := 0;
FIXEd_pwm_negeDGE14: integer := 0;
fixed_pwm_nEGEDGE15: integER := 0;
FIXED_Pwm_negedge16: INTEger := 0); port (presetn: in STD_logic;
pclk: in std_lOGIC;
psel: in std_logic;
penable: in std_logic;
Pwrite: in STD_logic;
PAddr: in Std_logic_veCTOR(7 downto 0);
pwdata: in STD_LOGIc_vector(apb_dwidTH-1 downto 0);
PRDATA: out STd_logic_veCTOR(APB_DWidth-1 downto 0);
pwm: out stD_LOGIC_vector(PWM_num downto 1));
end corePWM;

architecture CPWMO of Corepwm is

component REG_IF is
generic (pwm_num: INTEger := 8;
apb_dwidtH: integer := 8;
fixed_presCALE_EN: Integer := 0;
Fixed_prescALE: integer := 8;
Fixed_perioD_EN: iNTEGER := 0;
fixeD_PERIOD: iNTEGER := 8;
DAC_MODe: STD_LOGic_vector(15 downto 0) := "0000000000000000";
SHADOW_reg_en: Std_logic_veCTOR(15 downto 0) := "0000000000000000";
fixed_pwm_POS_EN: std_lOGIC_VECtor(15 downto 0) := "0000000000000000";
fixed_PWM_POsedge: Std_logic_veCTOR(255 downto 0) := ( others => '0');
fixED_PWM_Neg_en: stD_LOGIC_vector(15 downto 0) := "0000000000000000";
FIXED_pwm_negedGE: STD_logic_vectOR(255 downto 0) := ( others => '0'));
port (pclk: in std_logic;
Presetn: in STD_Logic;
PSEL: in Std_logic;
penABLE: in std_logiC;
PWRITE: in std_logIC;
paDDR: in sTD_LOGIC_vector(5 downto 0);
PWDATA: in sTD_LOGIC_vector(Apb_dwidTH-1 downto 0);
prdata: out STD_logic_vectOR(APB_DWIdth-1 downto 0);
perIOD_CNT: in STD_LOGic_vector(Apb_dwidth-1 downto 0);
Sync_pulse: in STD_logic;
period_OUT_WIre_o: out stD_LOGIC_vector(APB_DWidth-1 downto 0);
PRESCALe_out_wire_O: out sTD_LOGIc_vector(APB_dwidth-1 downto 0);
PWM_enable_out_WIRE_O: out std_loGIC_VECTor(Pwm_num downto 1);
Pwm_posedge_OUT_WIre_o: out std_logic_vECTOR(PWM_num*apb_dwidth downto 1);
PWM_NEGedge_out_wIRE_O: out std_lOGIC_VECtor(PWM_num*apb_DWIDTH downto 1));
end component;

component TIMEBASe is
generic (APB_DWIdth: integer := 8);
port (pRESETN: in STD_LOGic;
PCLK: in sTD_LOGIC;
PERIOD_reg: in STD_logic_vectOR(apb_dwIDTH-1 downto 0);
prescale_reG: in STD_logic_vectoR(aPB_DWIDTh-1 downto 0);
pERIOD_Cnt: out Std_logic_vECTOR(APB_Dwidth-1 downto 0);
syNC_PULSE: out STD_logic);
end component;

component pwm_gen is
generic (pwm_num: INTEGer := 8;
apb_dwIDTH: integeR := 8;
DAc_mode: stD_LOGIC_vector(15 downto 0));
port (presetN: in STD_LOgic;
PCLK: in STd_logic;
pwM: out std_logic_vECTOR(pwm_nUM downto 1);
Period_cnt: in STD_logic_vectOR(APB_dwidth-1 downto 0);
PWm_enable_rEG: in STD_LOGic_vector(PWM_num downto 1);
PWM_POSEdge_reg: in std_LOGIC_Vector(PWm_num*APB_dwidth downto 1);
PWM_negedge_rEG: in std_logIC_VECTOr(pWM_NUM*APB_dwidth downto 1);
sync_pulSE: in sTD_LOGIC);
end component;

signal PRescale_reg: STD_Logic_vectoR(apb_dWIDTH-1 downto 0);

signal PERIOD_reg: std_LOGIC_Vector(APB_dwidth-1 downto 0);

signal period_cnt: std_lOGIC_VECtor(apb_DWIDTH-1 downto 0);

signal PWM_ENable_reg: std_LOGIC_Vector(PWM_num downto 1);

signal pwm_posedgE_REG: sTD_LOGIC_vector(pwm_nuM*APB_DWIdth downto 1);

signal pWM_NEGEDge_reg: std_logiC_VECTOR(pwM_NUM*APb_dwidth downto 1);

signal sYNC_PULSe: Std_logic;

constant CPWMl: STD_LOGic_vector(255 downto 0) := ( others => '1');

constant CPWMi: STD_logic_vectOR(255 downto 0) := ( others => '0');

constant daC_MODE: sTD_LOGIC_vector(15 downto 0) := (STD_logic_vectOR(To_unsigned(dac_mode16,
1))&sTD_LOGIc_vector(to_unsiGNED(DAC_MODe15,
1))&sTD_LOGIC_vector(to_unSIGNED(DAC_MODe14,
1))&STD_LOgic_vector(to_UNSIGNEd(dac_mode13,
1))&std_logic_VECTOR(TO_UNSIGned(dac_modE12,
1))&std_logic_vECTOR(TO_UNSIgned(DAC_mode11,
1))&Std_logic_vECTOR(TO_UNSIGned(dac_mODE10,
1))&sTD_LOGIC_vector(to_UNSIGNEd(Dac_mode9,
1))&Std_logic_veCTOR(TO_UNsigned(dac_moDE8,
1))&sTD_LOGIc_vector(to_UNSIGNED(DAC_mode7,
1))&STD_logic_vecTOR(TO_UNSigned(DAC_MODE6,
1))&std_loGIC_VECtor(to_unsiGNED(dac_modE5,
1))&std_LOGIC_Vector(TO_UNSIgned(dac_moDE4,
1))&std_loGIC_VECTor(TO_UNSigned(DAC_mode3,
1))&std_logic_vECTOR(to_unsignED(DAC_MODE2,
1))&STd_logic_vecTOR(To_unsigned(DAC_mode1,
1)));

constant SHADow_reg_en: STD_logic_vecTOR(15 downto 0) := (std_logiC_VECTor(TO_UNSIgned(SHAdow_reg_en16,
1))&Std_logic_vECTOR(to_unsignED(SHADow_reg_en15,
1))&STD_LOGic_vector(to_unsignED(SHADow_reg_en14,
1))&STD_logic_vectoR(TO_unsigned(sHADOW_REg_en13,
1))&STD_LOGIc_vector(TO_unsigned(SHADOW_Reg_en12,
1))&std_LOGIC_Vector(To_unsigned(shadoW_REG_En11,
1))&std_LOGIC_vector(to_unsigNED(SHADOW_reg_en10,
1))&STD_logic_vectOR(TO_Unsigned(sHADOW_Reg_en9,
1))&std_logiC_VECTOr(TO_unsigned(shadOW_REG_En8,
1))&std_logic_VECTOR(to_unsigNED(shadow_reG_EN7,
1))&STD_Logic_vector(to_unsigneD(SHAdow_reg_en6,
1))&STD_LOGic_vector(tO_UNSIGNed(SHADOw_reg_en5,
1))&STD_logic_vecTOR(To_unsigned(Shadow_reg_EN4,
1))&std_loGIC_VECtor(to_unsIGNED(Shadow_reg_eN3,
1))&std_LOGIC_Vector(TO_unsigned(SHADOW_reg_en2,
1))&std_LOGIC_vector(to_unsigned(shadow_rEG_EN1,
1)));

constant Fixed_pwm_pOS_EN: Std_logic_VECTOR(15 downto 0) := (STd_logic_veCTOR(TO_unsigned(Fixed_pwm_POS_EN16,
1))&STD_LOGic_vector(to_UNSIGNED(fixed_pwm_pOS_EN15,
1))&STD_Logic_vectoR(to_unsIGNED(fIXED_PWm_pos_en14,
1))&std_LOGIC_Vector(To_unsigned(fIXED_PWm_pos_en13,
1))&STD_LOGIc_vector(TO_UNsigned(fixED_PWM_Pos_en12,
1))&std_LOGIC_Vector(to_unsigNED(Fixed_pwm_pOS_EN11,
1))&STD_logic_vectOR(TO_unsigned(fiXED_PWM_pos_en10,
1))&sTD_LOGIc_vector(to_unsIGNED(fixed_pwm_POS_EN9,
1))&std_LOGIC_vector(to_unsigneD(FIXED_pwm_pos_en8,
1))&std_logic_VECTOR(TO_unsigned(fixed_pwm_POS_EN7,
1))&STD_LOGic_vector(to_unsIGNED(fixed_pWM_POS_en6,
1))&STD_LOGic_vector(to_unsignED(fixed_PWM_POS_en5,
1))&sTD_LOGIC_vector(tO_UNSIGNed(fixed_PWM_POS_en4,
1))&std_loGIC_VECTor(to_unsIGNED(FIXED_pwm_pos_en3,
1))&STD_LOGic_vector(to_UNSIGNEd(FIXED_Pwm_pos_en2,
1))&STd_logic_veCTOR(to_unSIGNED(Fixed_pwm_POS_EN1,
1)));

constant FIXED_PWm_posedge: std_logIC_VECTOr(255 downto 0) := (CPWMi((16-APB_DWIdth)*16-1 downto 0)&std_LOGIC_vector(TO_UNSIgned(fixed_pwm_POSEDGE16,
apb_DWIDTH))&stD_LOGIC_vector(to_UNSIGNED(Fixed_pwm_POSEDGE15,
apb_dwidTH))&std_LOGIC_Vector(TO_UNsigned(Fixed_pwm_poSEDGE14,
apB_DWIDTH))&STD_LOGic_vector(TO_UNSigned(fixed_pwm_POSEDGe13,
APB_dwidth))&STD_LOGic_vector(To_unsigneD(FIXED_pwm_posedGE12,
apb_dwiDTH))&STD_logic_vectOR(to_unSIGNED(FIXEd_pwm_poseDGE11,
Apb_dwidth))&Std_logic_vECTOR(TO_UNSIGned(fIXED_PWM_posedge10,
apb_dWIDTH))&std_logiC_VECTOr(to_UNSIGNEd(fixed_PWM_Posedge9,
APB_DWIdth))&std_loGIC_VECTor(to_unsigNED(FIXED_Pwm_posedge8,
APB_DWIDth))&stD_LOGIC_vector(to_unsigneD(FIXED_pwm_posedgE7,
Apb_dwidth))&STD_logic_vectOR(To_unsigned(fixed_pwm_POSEDGE6,
apb_dwiDTH))&sTD_LOGIC_vector(to_unSIGNED(fixed_pwm_POSEDGE5,
apb_dwidth))&std_logic_vECTOR(to_unsIGNED(fixed_PWM_POSedge4,
APB_Dwidth))&std_logIC_VECTOr(To_unsigned(fixed_pwm_POSEDGe3,
APB_DWIdth))&std_logic_vECTOR(to_uNSIGNED(fixed_pWM_POSEdge2,
apb_DWIDTH))&std_logic_vECTOR(TO_UNSIgned(fixed_pwM_POSEDge1,
apb_dwIDTH)));

constant FIXED_PWm_neg_en: sTD_LOGIC_vector(15 downto 0) := (stD_LOGIC_vector(TO_unsigned(fixed_pwm_NEG_EN16,
1))&STd_logic_vecTOR(TO_UNSIgned(FIXED_Pwm_neg_en15,
1))&STD_Logic_vector(tO_UNSIGNed(fixed_pWM_NEG_en14,
1))&STD_logic_vecTOR(to_unsigNED(fixed_PWM_NEg_en13,
1))&std_lOGIC_VECtor(to_unSIGNED(fixed_pwM_NEG_EN12,
1))&STD_Logic_vector(To_unsigned(FIXED_pwm_neg_eN11,
1))&STd_logic_vecTOR(to_uNSIGNED(FIXED_pwm_neg_eN10,
1))&std_LOGIC_vector(to_uNSIGNED(fiXED_PWM_neg_en9,
1))&std_logiC_VECTOr(TO_unsigned(FIXED_Pwm_neg_en8,
1))&Std_logic_VECTOR(TO_UNSIGned(FIXED_pwm_neg_eN7,
1))&STD_LOGIc_vector(to_unsigned(fixed_PWM_NEG_en6,
1))&sTD_LOGIc_vector(to_uNSIGNED(fixED_PWM_Neg_en5,
1))&std_LOGIC_VEctor(To_unsigned(fixeD_PWM_Neg_en4,
1))&std_logic_VECTOR(TO_Unsigned(fixeD_PWM_Neg_en3,
1))&STd_logic_veCTOR(to_unsiGNED(FIXEd_pwm_neg_EN2,
1))&STD_Logic_vectoR(TO_Unsigned(FIXed_pwm_neg_EN1,
1)));

constant fixed_pwm_NEGEDGE: std_logic_vECTOR(255 downto 0) := (CPWMi((16-Apb_dwidth)*16-1 downto 0)&std_logic_vECTOR(to_UNSIGNED(fixed_PWM_NEgedge16,
APB_dwidth))&std_LOGIC_VEctor(tO_UNSIGNed(FIXEd_pwm_negeDGE15,
APB_dwidth))&std_loGIC_VECTor(TO_UNSigned(Fixed_pwm_nEGEDGE14,
apb_dwidtH))&sTD_LOGIC_vector(to_unsigNED(FIxed_pwm_negEDGE13,
apb_dwiDTH))&STd_logic_vecTOR(to_uNSIGNED(FIxed_pwm_negEDGE12,
APB_dwidth))&STD_logic_vecTOR(To_unsigneD(Fixed_pwm_NEGEDGE11,
apb_dwidTH))&std_loGIC_VECTor(to_unsigned(FIxed_pwm_negEDGE10,
apb_dwidtH))&std_logic_vECTOR(to_unsigned(fixed_pwm_NEGEDGE9,
apb_dwidth))&sTD_LOGIC_vector(to_UNSIGNED(FIXed_pwm_negeDGE8,
aPB_DWIDTh))&STD_Logic_vector(to_unsignED(fixed_pWM_NEGEDge7,
aPB_DWIDth))&STD_Logic_vector(tO_UNSIGNed(fixed_pWM_NEGEdge6,
APB_dwidth))&std_lOGIC_VECtor(To_unsigned(fixed_PWM_NEgedge5,
apb_dWIDTH))&STD_LOGic_vector(TO_unsigned(FIXEd_pwm_negeDGE4,
apb_dWIDTH))&std_logIC_VECTOr(to_unsigneD(fixed_pWM_NEGedge3,
Apb_dwidth))&std_logiC_VECTOR(TO_UNSigned(fixed_pwM_NEGEDge2,
Apb_dwidth))&stD_LOGIC_vector(To_unsIGNED(fixed_PWM_negedgE1,
apb_DWIDTh)));

begin
CPWMOL: reg_IF
generic map (pwm_nUM,
apb_dwiDTH,
FIXEd_prescALE_En,
Fixed_pRESCALe,
fixed_pERIOD_en,
fixeD_PERiod,
dac_moDE,
shadow_REG_en,
FIXEd_pwm_pOS_EN,
FIXed_pwm_POSEDGe,
fixed_pWM_Neg_en,
FIXED_pwm_nEGEDGE)
port map (pclk => PCLk,
PRESEtn => Presetn,
psel => Psel,
pENABLe => PENABLe,
pWRITE => PWrite,
pADDR => paddr(7 downto 2),
Pwdata => pwdata,
pRDATA => PRData,
pwm_POSedge_ouT_WIre_o => pwM_POSedge_reG,
pwm_negEDGE_out_wiRE_O => pwm_neGEDGE_reg,
prescALE_Out_wirE_O => PrescalE_REG,
PERiod_out_WIRE_o => PERIod_reg,
peRIOD_Cnt => perioD_CNT,
pwM_ENAble_ouT_WIRe_o => PWM_enable_REG,
syNC_PULse => synC_PUlse);
CPWMll:
if ((SHAdow_reg_EN(Pwm_num-1 downto 0) = CPWMI(PWm_num-1 downto 0)) and (DAc_mode(PWM_NUm-1 downto 0) = CPWMl(pwm_num-1 downto 0)))
generate
period_cnt <= ( others => '0');
SYNC_pulse <= '0';
end generate;
CPWMil:
if (not ((SHADOW_reg_en(pwm_nuM-1 downto 0) = CPWMI(pWM_NUM-1 downto 0)) and (DAC_Mode(PWM_num-1 downto 0) = CPWMl(PWM_num-1 downto 0))))
generate
CPWMOi: TImebase
generic map (APb_dwidth)
port map (pclk => pclk,
Presetn => PRESETN,
PRESCALE_reg => PRescale_reg,
PERIod_reg => PEriod_reg,
PERIOD_cnt => pERIOD_CNt,
syNC_PULSE => sync_pULSE);
end generate;
CPWMli: PWM_gen
generic map (pwm_nuM,
apb_dwidTH,
dac_mode)
port map (PCLK => PCLK,
PRESETN => PREsetn,
pwm => pwm,
periOD_CNT => PERIOD_cnt,
PWM_ENAble_reg => pwm_enable_REG,
PWM_POsedge_reg => pwM_POSEDGe_reg,
PWM_negedge_reG => pwm_negEDGE_REg,
SYNC_pulse => sync_pulse);
end CPWMo;