?? support.vhd
字號:
constant input20: integer := 16#1000000#;
constant INPUt21: INTEGEr := 16#2000000#;
constant input22: INTeger := 16#4000000#;
constant input23: integer := 16#8000000#;
constant INPUt24: inTEGER := 16#10000000#;
constant INput25: INTEGER := 16#20000000#;
constant Input26: INTEGER := 16#40000000#;
constant Input27: INTEGER := 16#40000000#;
constant ANYINput: intEGER := 16#7FFFFFF0#;
constant ilOADLOOP: integer := 256*24;
constant iDECLOOP: integer := 256*25;
constant iINCLOOP: INTEger := 256*26;
constant ILOOPZ: integeR := 16#08#;
constant LOOPZ: Integer := 16#08#;
constant EN_USER: integER range 0 to 1 := 0;
end support;
library IEEE;
use iEEE.STd_logic_1164.all;
use ieee.std_logiC_ARITH.all;
use ieee.STD_LOGic_unsigNED.all;
package body SUPPort is
function doins(s1: iNTEGER;
ABClio0: integer;
ABCiio0: INTeger;
ABCo0o0: INTEGER;
ABCL0O0: inteGER)
return std_logic_VECTOR is
begin
return (ABCilo0(5,
S1,
ABClio0,
ABCiio0,
ABCo0o0,
ABCl0o0));
end Doins;
function doins(S1: Integer;
ABCLIO0: integer;
ABCiio0: INTEGer;
ABCO0O0: integer)
return std_lOGIC_VEctor is
begin
return (ABCilO0(4,
s1,
ABCLio0,
ABCiio0,
ABCO0O0,
-1));
end doins;
function doins(s1: inteGER;
ABCLIO0: inteGER;
ABCiio0: INTEGEr)
return Std_logic_vECTOR is
begin
return (ABCILO0(3,
s1,
ABClio0,
ABCiio0,
-1,
-1));
end DOINs;
function DOINS(s1: iNTEGER;
ABCLIO0: inteGER)
return stD_LOGIC_vector is
begin
return (ABCiLO0(2,
S1,
ABClio0,
-1,
-1,
-1));
end doiNS;
function doinS(s1: integer)
return STD_logic_veCTOR is
begin
return (ABCILO0(1,
s1,
-1,
-1,
-1,
-1));
end DOINS;
function Chartoint(c: CHARActer)
return INTEGer is
begin
return (cHARACTER'POS(C));
end chaRTOINT;
function ABCI01i(ABCO11i,ABCl11I,ABCI11i,ABCooO0,ABCLOo0: std_logIC_VECTor)
return STD_LOGic_vector is
variable insTRUCTION: STD_Logic_vectOR(32+16+4+6-1 downto 0);
begin
INSTRUCtion := ABCloo0&ABCooo0&ABCi11i&ABCl11i&ABCO11I;
return (INStruction);
end ABCI01I;
function ABCILO0(ABCoio0: INTEGER;
S1: INTEGER;
ABClio0: INTEger;
ABCiio0: INTEGEr;
ABCo0o0: INTEGER;
ABCl0o0: integER)
return std_lOGIC_VEctor is
variable ABCo11i: std_loGIC_VECtor(2 downto 0);
variable ABCl11I: std_LOGIC_Vector(2 downto 0);
variable ABCi11I: std_LOGIC_vector(3 downto 0);
variable ABCOOO0: STD_Logic_vectOR(15 downto 0);
variable ABCLOO0: STD_logic_vectOR(31 downto 0);
constant ABCo1o0: stD_LOGIC_vector(31 downto 0) := ( others => '1');
constant Zero: STD_LOGic_vectoR(31 downto 0) := ( others => '0');
variable ABCl1O0: INTEGER;
variable FFW: integer;
begin
ABCo11I := "---";
ABCL11i := "---";
ABCi11i := ( others => '-');
ABCooo0 := ( others => '-');
ABCLOO0 := ( others => '-');
ABCl1o0 := s1/256;
FFW := s1-ABCL1O0*256;
ABCl1o0 := ABCL1O0*256;
case ABCl1o0 is
when iload =>
ABCo11i := "000";
ABCl11i := "111";
ABCi11i(0) := '0';
ABCloo0 := conv_STD_LOgic_vecTOR(ABCLIO0,
32);
if ABCoio0 >= 3 then
case ABCLIO0 is
when IDAT =>
ABCLOO0 := CONV_Std_logic_VECTOR(ABCIIO0,
32);
when IDat8 =>
ABCloo0 := conv_sTD_LOGIc_vectoR(ABCIIO0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCloo0 := Conv_std_lOGIC_VEctor(ABCIIO0,
32);
ABCloo0(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCloo0 := conv_STD_LOGic_vectOR(ABCiio0,
32);
when iram =>
ABCOOO0(7 downto 0) := CONV_std_logiC_VECTor(ABCIIO0,
8);
ABCI11i(0) := '1';
ABCloO0 := ( others => '-');
when others =>
end case;
end if;
when iincb =>
if FFW > 0 then
ABCO11I := "000";
ABCl11i := "100";
ABCi11i(0) := '0';
ABCloo0 := COnv_std_loGIC_VECtor(1,
32);
else
ABCO11I := "000";
ABCL11i := "000";
ABCI11i(0) := '0';
end if;
when idec =>
ABCO11i := "000";
ABCl11I := "100";
ABCi11i(0) := '0';
ABCLOO0 := ( others => '1');
when IAND =>
ABCO11I := "000";
ABCl11I := "001";
ABCi11i(0) := '0';
ABCLOO0 := CONV_std_logic_VECTOr(ABClio0,
32);
if ABCOIO0 >= 3 then
case ABCLIO0 is
when idat =>
ABCLOO0 := conv_STD_LOGIc_vectoR(ABCIIo0,
32);
when iDAT8 =>
ABClOO0 := COnv_std_logIC_VECtor(ABCIio0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idAT16 =>
ABCLOo0 := conv_STD_LOGic_vectOR(ABCIIO0,
32);
ABCLoo0(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCLOO0 := CONV_std_logiC_VECTor(ABCiio0,
32);
when IRAm =>
ABCooo0(7 downto 0) := CONV_STd_logic_VECTOR(ABCiio0,
8);
ABCi11i(0) := '1';
ABCLoo0 := ( others => '-');
when others =>
end case;
end if;
when IOR =>
ABCo11i := "000";
ABCl11i := "010";
ABCI11I(0) := '0';
ABCLOO0 := CONV_std_logic_VECTOr(ABClIO0,
32);
if ABCoio0 >= 3 then
case ABClio0 is
when idaT =>
ABCloO0 := CONv_std_logiC_VECTor(ABCIIO0,
32);
when idat8 =>
ABCloo0 := CONV_STd_logic_VECTOR(ABCiio0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCLoo0 := coNV_STD_Logic_veCTOR(ABCiio0,
32);
ABCLOO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLOO0 := CONV_std_logic_VECTOr(ABCiio0,
32);
when IRAM =>
ABCOOO0(7 downto 0) := CONV_STd_logic_VECTOR(ABCiio0,
8);
ABCi11i(0) := '1';
ABCloo0 := ( others => '-');
when others =>
end case;
end if;
when ixor =>
ABCO11i := "000";
ABCl11i := "011";
ABCI11I(0) := '0';
ABCloo0 := Conv_std_loGIC_VEctor(ABClio0,
32);
if ABCOIO0 >= 3 then
case ABCLIO0 is
when Idat =>
ABCLOO0 := Conv_std_loGIC_VEctor(ABCiiO0,
32);
when IDAT8 =>
ABCloo0 := cONV_STD_logic_veCTOR(ABCiio0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when IDAT16 =>
ABCloo0 := conv_std_lOGIC_Vector(ABCiio0,
32);
ABCloo0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLOO0 := CONV_STd_logic_VECTOR(ABCiio0,
32);
when IRAM =>
ABCOOO0(7 downto 0) := conv_std_LOGIC_vector(ABCIIO0,
8);
ABCi11I(0) := '1';
ABCloo0 := ( others => '-');
when others =>
end case;
end if;
when IADd =>
ABCo11i := "000";
ABCl11i := "100";
ABCi11i(0) := '0';
ABCLOO0 := CONV_std_logic_VECTOr(ABCLIO0,
32);
if ABCoio0 >= 3 then
case ABClio0 is
when idat =>
ABCLOO0 := CONV_std_logiC_VECTor(ABCiio0,
32);
when idAT8 =>
ABCloo0 := conv_STD_LOGic_vectOR(ABCiio0,
32);
ABClOO0(31 downto 8) := ( others => '-');
when IDAT16 =>
ABClOO0 := conv_STD_LOGic_vectOR(ABCiio0,
32);
ABCloo0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLOO0 := CONV_STD_LOGIC_vector(ABCiio0,
32);
when iram =>
ABCooo0(7 downto 0) := CONV_std_logiC_VECTor(ABCiio0,
8);
ABCI11i(0) := '1';
ABCLOO0 := ( others => '-');
when others =>
end case;
end if;
when iMULT =>
ABCo11i := "000";
ABCl11i := "000";
ABCi11i(0) := '0';
ABCLOo0 := CONv_std_logiC_VECTor(ABClio0,
32);
if ABCOIO0 >= 3 then
case ABCLio0 is
when IDat =>
ABCLOO0 := conV_STD_Logic_vecTOR(ABCiio0,
32);
when IDAT8 =>
ABCloO0 := COnv_std_logIC_VECtor(ABCiIO0,
32);
ABCLOO0(31 downto 8) := ( others => '-');
when Idat16 =>
ABCLOO0 := CONV_STd_logic_vECTOR(ABCIio0,
32);
ABCLOo0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCloo0 := conv_std_LOGIC_vector(ABCiio0,
32);
when iram =>
ABCOoo0(7 downto 0) := conV_STD_Logic_vecTOR(ABCIIO0,
8);
ABCi11i(0) := '1';
ABCloo0 := ( others => '-');
when others =>
end case;
end if;
when ISub =>
ABCO11i := "000";
ABCl11I := "100";
ABCi11i(0) := '0';
ABCLOO0 := not (Conv_std_lOGIC_VEctor(ABClio0,
32)-1);
if ABCOIO0 >= 3 then
ABCloo0 := not (conv_std_lOGIC_VEctor(ABCiio0,
32)-1);
case ABClio0 is
when iDAT =>
when idat8 =>
ABCloo0(31 downto 8) := ( others => '1');
when IDAT16 =>
ABCloo0(31 downto 16) := ( others => '1');
when IDAT32 =>
when IRAM =>
ABCooo0(7 downto 0) := conv_stD_LOGIC_vector(ABCIIO0,
8);
ABCi11I(0) := '1';
ABCloo0 := ( others => '-');
when others =>
end case;
end if;
when ishl0 =>
ABCO11I := "000";
ABCl11I := "101";
ABCLOO0(1 downto 0) := "00";
ABCI11i(0) := '0';
when ishl1 =>
ABCO11i := "000";
ABCl11i := "101";
ABCloo0(1 downto 0) := "01";
ABCi11i(0) := '0';
when ishle =>
ABCo11i := "000";
ABCl11i := "101";
ABCLOO0(1 downto 0) := "10";
ABCI11i(0) := '0';
when irol =>
ABCo11i := "000";
ABCl11i := "101";
ABCloo0(1 downto 0) := "11";
ABCI11i(0) := '0';
when ishr0 =>
ABCo11i := "000";
ABCl11i := "110";
ABCLoo0(1 downto 0) := "00";
ABCi11i(0) := '0';
when isHR1 =>
ABCO11i := "000";
ABCl11i := "110";
ABCLOO0(1 downto 0) := "01";
ABCi11i(0) := '0';
when isHRE =>
ABCO11I := "000";
ABCL11I := "110";
ABCLOO0(1 downto 0) := "10";
ABCI11I(0) := '0';
when IRor =>
ABCo11i := "000";
ABCl11i := "110";
ABCloo0(1 downto 0) := "11";
ABCi11i(0) := '0';
when ICMP =>
ABCO11i := "001";
ABCL11i := "011";
ABCi11i(0) := '0';
ABCloo0 := conv_std_lOGIC_Vector(ABClio0,
32);
if ABCoio0 >= 3 then
case ABClio0 is
when IDAT =>
ABCLOO0 := conv_std_lOGIC_VEctor(ABCiio0,
32);
when Idat8 =>
ABCloo0 := conv_stD_LOGIC_vector(ABCiio0,
32);
ABCLoo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCloo0 := conv_std_lOGIC_Vector(ABCiio0,
32);
ABCLOO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCloo0 := Conv_std_lOGIC_VEctor(ABCiio0,
32);
when IRAM =>
ABCoOO0(7 downto 0) := CONV_std_logiC_VECTor(ABCiio0,
8);
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when others =>
end case;
end if;
when Icmpleq =>
ABCo11I := "001";
ABCL11I := "100";
ABCi11I(0) := '0';
ABCLoo0 := not (conv_sTD_LOGIc_vector(ABClio0,
32)-1);
if ABCOIO0 >= 3 then
ABCloO0 := not (cONV_STD_logic_veCTOR(ABCIIO0,
32)-1);
case ABClio0 is
when IDAT =>
when idat8 =>
ABCloo0(31 downto 8) := ( others => '1');
when idat16 =>
ABCLOO0(31 downto 16) := ( others => '1');
when IDAT32 =>
when iram =>
ABCooo0(7 downto 0) := conv_std_LOGIC_vector(ABCiIO0,
8);
ABCi11i(0) := '1';
ABCloo0 := ( others => '-');
when others =>
end case;
end if;
when IBitclr =>
ABCo11i := "000";
ABCL11i := "001";
ABCloo0 := ABCO1O0;
ABCLOO0(ABCLIO0) := '0';
ABCI11i(0) := '0';
when IBITSET =>
ABCo11i := "000";
ABCL11I := "010";
ABCloo0 := zerO;
ABCLOO0(ABClio0) := '1';
ABCI11i(0) := '0';
when IBIttst =>
ABCo11i := "001";
ABCl11I := "001";
ABCLOO0 := zERO;
ABCloo0(ABCLIO0) := '1';
ABCI11i(0) := '0';
when IAPBReadz =>
ABCo11i := "010";
ABCL11I := "111";
ABCi11i := CONv_std_logIC_VECTor(ABClio0,
4);
when IAPBWRTz =>
ABCO11i := "010";
ABCL11I := "---";
ABCI11i := CONV_STd_logic_VECTOR(ABCIIO0,
4);
case ABClio0 is
when IACM =>
ABCL11I := "110";
when iacC =>
ABCl11i := "100";
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