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?? Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P
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when IDAT =>
ABCL11i := "101";
ABCLOO0 := CONV_std_logiC_VECTor(ABCo0o0,
32);
when idat8 =>
ABCl11I := "101";
ABCloo0 := CONV_std_logic_VECTOr(ABCo0o0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCL11I := "101";
ABCloO0 := conv_stD_LOGIC_vector(ABCO0O0,
32);
ABCLoo0(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCl11I := "101";
ABCLOO0 := conv_STD_LOGic_vectoR(ABCo0o0,
32);
when others =>
end case;
when Iapbread =>
ABCO11i := "010";
ABCL11i := "011";
ABCi11I := CONV_std_logiC_VECTor(ABCLIO0,
4);
ABCooO0 := Conv_std_loGIC_VECtor(ABCIIo0,
16);
when IAPbwrt =>
ABCO11I := "010";
ABCL11I := "---";
ABCi11i := Conv_std_loGIC_VEctor(ABCiio0,
4);
ABCooo0 := CONV_std_logiC_VECTOr(ABCO0O0,
16);
case ABClio0 is
when Iacm =>
ABCL11I := "010";
when IACC =>
ABCl11I := "000";
when IDAT =>
ABCl11I := "001";
ABCloo0 := conv_STD_LOgic_vectOR(ABCL0O0,
32);
when idat8 =>
ABCl11i := "001";
ABCLOo0 := conv_std_lOGIC_Vector(ABCl0o0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCl11I := "001";
ABCloo0 := cONV_STD_logic_veCTOR(ABCL0O0,
32);
ABCloO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCL11I := "001";
ABCloo0 := CONV_std_logic_VECTOr(ABCL0O0,
32);
when others =>
end case;
when ILOadz =>
ABCo11I := "011";
ABCl11i := "000";
ABCI11I(0) := '0';
case ABCLio0 is
when iacc =>
ABCi11i(0) := '1';
ABCloo0 := ( others => '-');
when Idat =>
ABCloo0 := conv_std_LOGIC_vector(ABCIIO0,
32);
when idat8 =>
ABCloo0 := CONv_std_logiC_VECTor(ABCIIo0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCloo0 := CONV_Std_logic_VECTOR(ABCiio0,
32);
ABCloo0(31 downto 16) := ( others => '-');
when iDAT32 =>
ABCloo0 := CONV_std_logic_VECTOr(ABCIIO0,
32);
when others =>
end case;
when IINCZ =>
ABCO11I := "011";
ABCl11i := "001";
ABCi11i(0) := '0';
ABCloo0 := CONV_std_logic_VECTOr(1,
32);
when idECZ =>
ABCO11i := "011";
ABCl11i := "001";
ABCi11i(0) := '0';
ABCLOo0 := ( others => '1');
when iaddz =>
ABCO11I := "011";
ABCL11I := "001";
ABCI11I(0) := '0';
case ABClio0 is
when iacC =>
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when idat =>
ABCloo0 := cONV_STD_logic_veCTOR(ABCiiO0,
32);
when idat8 =>
ABClOO0 := CONV_std_logic_VECTOr(ABCiio0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCLOO0 := CONv_std_logIC_VECtor(ABCiio0,
32);
ABCLoo0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCloo0 := CONV_Std_logic_VECTOR(ABCiio0,
32);
when others =>
end case;
when ISUBz =>
ABCO11I := "011";
ABCl11i := "001";
ABCi11I(0) := '0';
case ABCLIO0 is
when IACC =>
ABCi11I(0) := '1';
ABCloo0 := ( others => '-');
when idaT =>
ABCloo0 := not (CONV_Std_logic_VECTOR(ABCiio0,
32)-1);
when idaT8 =>
ABCLOO0 := not (CONV_std_logiC_VECTor(ABCiIO0,
32)-1);
when IDAT16 =>
ABCloo0 := not (conv_std_LOGIC_vector(ABCIIO0,
32)-1);
when iDAT32 =>
ABCloo0 := not (CONV_std_logic_VECTOr(ABCiio0,
32)-1);
when others =>
end case;
when IIOWRT =>
ABCo11i := "011";
ABCl11i := "111";
ABCi11i(0) := '0';
case ABCLIO0 is
when iacc =>
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when iDAT =>
ABCLoo0 := conv_std_LOGIC_Vector(ABCiio0,
32);
when idat8 =>
ABCLOO0 := coNV_STD_logic_veCTOR(ABCiio0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCloo0 := conv_std_LOGIC_vector(ABCIio0,
32);
ABCLOO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCLOO0 := conv_sTD_LOGIc_vectoR(ABCiio0,
32);
when others =>
end case;
when IIORead =>
ABCO11i := "011";
ABCL11I := "110";
when iramrEAD =>
ABCO11I := "011";
ABCl11I := "011";
ABCOOO0 := coNV_STD_logic_veCTOR(ABClio0,
16);
when irAMWRT =>
ABCo11i := "011";
ABCl11I := "010";
ABCOOo0 := CONV_STd_logic_vECTOR(ABClio0,
16);
ABCi11i(0) := '1';
if ABCoio0 >= 3 then
ABCi11i(0) := '0';
ABCOOO0 := cONV_STD_logic_veCTOR(ABClIO0,
16);
case ABCiiO0 is
when iacc =>
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when iDAT =>
ABCloo0 := Conv_std_lOGIC_VEctor(ABCo0o0,
32);
when idat8 =>
ABCLOO0 := CONV_std_logiC_VECTor(ABCo0o0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when idat16 =>
ABCLOO0 := CONV_std_logiC_VECTOr(ABCo0o0,
32);
ABCloO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCloo0 := CONV_STD_logic_vECTOR(ABCO0O0,
32);
when others =>
end case;
end if;
when ipush =>
ABCo11i := "011";
ABCl11i := "100";
ABCI11I(0) := '0';
case ABClio0 is
when blank =>
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when iacc =>
ABCi11i(0) := '1';
ABCLOO0 := ( others => '-');
when idat =>
ABCloo0 := Conv_std_lOGIC_VEctor(ABCIIO0,
32);
when IDAT8 =>
ABCLOO0 := conv_STD_LOgic_vectOR(ABCIIo0,
32);
ABCloo0(31 downto 8) := ( others => '-');
when IDAT16 =>
ABCLOO0 := coNV_STD_Logic_vecTOR(ABCiio0,
32);
ABCLOO0(31 downto 16) := ( others => '-');
when IDAT32 =>
ABCloO0 := CONV_std_logic_VECTOr(ABCiio0,
32);
when others =>
end case;
when IPOP =>
ABCo11i := "011";
ABCL11I := "101";
when Ijumpb =>
ABCo11i := "100";
ABCL11I := "-01";
if ABCoio0 >= 4 then
ABCl11i(0) := ABClL1(ABCLio0);
ABCloo0 := conv_std_lOGIC_VEctor(ABCIIo0,
32);
ABCOOo0 := CONV_STD_logic_veCTOR(ABCO0O0,
16);
else
ABCloo0(0) := '1';
ABCOoo0 := conv_STD_LOgic_vectOR(ABCLIO0,
16);
end if;
ABCloo0(31 downto FFW+4) := ( others => '-');
when iwaitb =>
ABCo11i := "100";
ABCl11i := "-11";
if ABCoio0 >= 3 then
ABCL11i(0) := ABCLl1(ABClio0);
ABCloo0 := conv_std_LOGIC_Vector(ABCiio0,
32);
else
ABCloo0(0) := '1';
end if;
ABCLoo0(31 downto FFW+4) := ( others => '-');
when iCALLB =>
ABCO11I := "101";
ABCl11i := "-01";
if ABCoio0 >= 4 then
ABCl11I(0) := ABCll1(ABClio0);
ABCloO0 := conv_STD_LOGic_vectoR(ABCiio0,
32);
ABCooo0 := conv_sTD_LOGIc_vectoR(ABCo0o0,
16);
else
ABCloo0(0) := '1';
ABCOOO0 := conv_STD_LOGic_vectoR(ABClio0,
16);
end if;
ABCloo0(31 downto FFW+4) := ( others => '-');
when IRETurnb =>
ABCo11I := "110";
ABCl11i := "-01";
if ABCoio0 >= 3 then
ABCl11i(0) := ABCll1(ABCLIO0);
ABCLOO0 := COnv_std_loGIC_VECtor(ABCIIO0,
32);
else
ABCLOO0(0) := '1';
end if;
ABCloO0(31 downto FFW+4) := ( others => '-');
when irETISRB =>
ABCO11I := "110";
ABCl11i := "-11";
if ABCOIO0 >= 3 then
ABCl11i(0) := ABClL1(ABCLIO0);
ABCloo0 := coNV_STD_Logic_veCTOR(ABCiio0,
FFW);
else
ABCLOo0(0) := '1';
end if;
ABCLOO0(31 downto FFW+4) := ( others => '-');
when INOP =>
ABCo11i := "111";
if EN_USER = 1 then
ABCL11i := "000";
end if;
when iuser =>
ABCo11i := "111";
ABCL11i(0) := '1';
ABCl11I := cONV_STD_logic_veCTOR(ABClio0,
3);
ABCLOo0 := conv_sTD_LOGIc_vectoR(ABCiIO0,
32);
ABCOOo0 := cONV_STD_logic_veCTOR(ABCO0O0,
16);
ABCi11i := CONV_STD_logic_vECTOR(ABCl0o0,
4);
when others =>
end case;
return (ABCi01i(ABCo11i,
ABCL11i,
ABCi11I,
ABCooo0,
ABCloo0));
end ABCilo0;
function MAX(a,b: INTEger)
return INTEGER is
begin
if a > b then
return (a);
else
return (B);
end if;
end max;
function MIN(A,B: INTeger)
return intEGER is
begin
if A < B then
return (a);
else
return (b);
end if;
end min;
function ABCLl1(ABCioo0: Integer)
return Std_logic is
begin
if ABCIOO0 /= 0 then
return ('1');
else
return ('0');
end if;
end ABCLL1;
function ABCLL1(ABCIOO0: boolean)
return STD_logic is
begin
if ABCIOO0 then
return ('1');
else
return ('0');
end if;
end ABCll1;
function ABColo0(EN_RAM,EN_CALL,DWidth,ICWIDTH: INTEGer)
return integeR is
variable ABCl0I,ABCo1i: INteger;
begin
ABCL0I := 0;
ABCo1i := 0;
if EN_CALL = 1 then
ABCo1I := 8;
if ICWIDTH > 8 then
ABCo1i := 16;
end if;
end if;
if EN_RAM = 1 then
ABCL0I := dwidTH;
end if;
if ABCl0i > ABCo1i then
return (ABCl0i);
elsif ABCo1i > 0 then
return (ABCO1I);
else
return (1);
end if;
end ABCOLO0;
function calc_sWIDTH(X: integeR)
return INTEGEr is
begin
if X >= 9 then
return (4);
elsif X >= 5 then
return (3);
elsif X >= 3 then
return (2);
elsif x >= 2 then
return (1);
else
return (0);
end if;
end CALC_swidth;
function LOG2R(x: INTEGer)
return integer is
begin
if X >= 65536 then
return (17);
elsif X >= 32768 then
return (16);
elsif x >= 16384 then
return (15);
elsif x >= 8192 then
return (14);
elsif x >= 4096 then
return (13);
elsif X >= 2048 then
return (12);
elsif x >= 1024 then
return (11);
elsif X >= 512 then
return (10);
elsif X >= 256 then
return (9);
elsif x >= 128 then
return (8);
elsif X >= 64 then
return (7);
elsif x >= 32 then
return (6);
elsif X >= 16 then
return (5);
elsif X >= 8 then
return (4);
elsif X >= 4 then
return (3);
elsif X >= 2 then
return (2);
elsif x >= 1 then
return (1);
else
return (1);
end if;
end log2r;
function CALC_initwidth(AWIdth,DWIDTH,ABCllo0,ICWIDTH: Integer)
return inteGER is
variable SWidth: INTEGEr;
variable ABCii0: INTEGER;
variable ABCO00: integer;
variable ABCl00: INTEGER;
variable ABCi00: INTEGER;
variable ABCi1O0: integeR;
variable ABCOol0: INTEGEr;
variable ABCLOl0: intEGER;
begin
if ABCllo0 = 0 then
swidth := CALC_swidth(ABCLLO0);
else
swidth := 1;
end if;
ABCII0 := 2**ICWIDTH;
ABCO00 := AWIDth+dwidth+SWIDTH+6;
ABCl00 := 1+(ABCiI0-1)/512;
ABCi00 := 1+(ABCo00-1)/9;
ABCi1o0 := ABCi00*ABCL00;
ABCOol0 := ABCI1o0*512;
ABCLOL0 := LOG2R(ABCOOL0);
if ABClol0 > 16 then
ABCLol0 := 16;
end if;
return (ABClol0);
end calc_INITWIDTh;
function cleAN(x: Std_logic_vECTOR)
return Std_logic_vECTOR is
variable ABCioo0: STD_logic_vectOR(x'range );
begin
ABCioo0 := X;
-- synthesis translate_off
ABCioo0 := ( others => '0');
for ABCLL in ABCIoo0'range
loop
if X(ABCLl) = '1' then
ABCioo0(ABCll) := '1';
end if;
end loop;
-- synthesis translate_on
return (ABCioo0);
end clean;
end SUPport;
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