-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library ieee;
use iEEE.STD_logic_1164.all;
library fusion;
entity IRAM512x9 is
generic (id: Integer;
CID: integer;
RID: INTEGER); port (RWCLK: in std_LOGIC;
RESET: in STD_LOgic;
renaBLE: in STD_LOGIc;
Raddr: in STD_LOgic_vectoR(8 downto 0);
RD: out sTD_LOGIc_vector(8 downto 0);
INITADDR: in std_logiC_VECTOr(8 downto 0);
Wenable: in STD_Logic;
INITDATA: in std_lOGIC_VEctor(8 downto 0));
end iram512X9;

architecture RTL of iram512x9 is

component RAM4k9
generic (MEMoryfile: string := "");
port (addra11,ADDra10,addra9,ADDRA8,ADDRa7,ADDra6,ADDra5,ADDra4,ADDRA3,ADDRA2,ADDRA1,adDRA0,addrb11,addrb10,ADDRb9,addRB8,ADDRb7,addrb6,ADDRB5,addrb4,addrb3,addrb2,addrb1,aDDRB0,diNA8,dINA7,dina6,dina5,DINA4,dinA3,Dina2,dINA1,DINa0,dinb8,DINB7,dinb6,dinb5,dinb4,dinb3,dinB2,dinb1,dinb0,widtha0,widTHA1,wiDTHB0,WIDTHB1,piPEA,pipeb,WMODEA,wmODEB,Blka,blkB,weNA,wenb,clka,clkb,Reset: in std_logic := 'U';
dOUTA8,DOUTA7,dOUTA6,douTA5,douta4,DOuta3,DOUTA2,douTA1,DOuta0,dOUTB8,Doutb7,DOUTB6,DOUtb5,doutb4,doutb3,dOUTB2,DOUTB1,DOUTB0: out std_logIC);
end component;

signal ABCi0ii,ABCO1ii,ABCl1ll,ABCi1LL: STd_logic;

-- synthesis translate_off
constant ABCi0LL: string(1 to 14) := "RAMABC_"&CHARACter'VAL(ID+48)&cHARACTEr'VAl(rid+48)&charactER'val(cid+48)&".mem";

-- synthesis translate_on
begin
ABCL1LL <= '1';
ABCI1LL <= '0';
ABCO1ii <= not renable;
ABCI0II <= not Wenable;
Iram: ram4k9
-- synthesis translate_off
generic map (memoryfILE => ABCi0ll)
-- synthesis translate_on
port map (addra11 => ABCI1LL,
ADDRA10 => ABCI1ll,
addra9 => ABCi1LL,
addRA8 => INITADDR(8),
ADDRA7 => INITADDR(7),
ADDRa6 => INITADDR(6),
addrA5 => INITADDR(5),
addra4 => INITADDR(4),
ADdra3 => INITADDR(3),
ADDRA2 => INITADDR(2),
ADDRA1 => INITADDR(1),
ADDRA0 => INITADDR(0),
ADDRB11 => ABCi1ll,
ADDRb10 => ABCi1ll,
Addrb9 => ABCI1Ll,
addrb8 => raddr(8),
ADDRB7 => raddr(7),
addrb6 => rADDR(6),
ADDrb5 => rADDR(5),
adDRB4 => RADDR(4),
addrb3 => raddr(3),
addRB2 => RAddr(2),
addrb1 => RADDR(1),
ADDRB0 => Raddr(0),
DINA8 => INITDATA(8),
DINA7 => INITDATA(7),
dina6 => INITDATA(6),
dina5 => INITDATA(5),
dina4 => INITDATA(4),
dINA3 => INITDATA(3),
dINA2 => INITDATA(2),
dina1 => INITDATA(1),
DINA0 => INITDATA(0),
DInb8 => ABCi1ll,
DINB7 => ABCi1LL,
dinb6 => ABCI1LL,
DINB5 => ABCI1LL,
DInb4 => ABCI1LL,
dinb3 => ABCi1LL,
dINB2 => ABCI1ll,
DINB1 => ABCi1ll,
dinb0 => ABCi1ll,
WIDTHA0 => ABCl1ll,
widtha1 => ABCL1ll,
widthb0 => ABCL1LL,
WIDTHb1 => ABCl1ll,
PIPEA => ABCi1ll,
PIPEb => ABCi1LL,
wMODEA => ABCI1LL,
wMODEB => ABCi1LL,
blkA => ABCi0ii,
BLKB => ABCO1Ii,
wena => ABCi1LL,
WENb => ABCl1lL,
CLka => rwclk,
CLKB => RWCLK,
Reset => RESET,
DOUTA8 => open ,
Douta7 => open ,
DOUTA6 => open ,
douta5 => open ,
DOUTA4 => open ,
doUTA3 => open ,
DOUTA2 => open ,
douta1 => open ,
DOUTA0 => open ,
DOUtb8 => rd(8),
DOUTB7 => rd(7),
DOutb6 => RD(6),
doutb5 => RD(5),
DOUtb4 => Rd(4),
DOUTB3 => rd(3),
doutb2 => rd(2),
DOutb1 => Rd(1),
doUTB0 => RD(0));
end rTL;