-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library IEee;
use ieee.STd_logic_1164.all;
use IEEE.stD_LOGIC_arith.all;
use IEEE.std_logiC_UNSIGned.all;
use work.SUPPort.all;
entity ABCli0i is
generic (Dwidth: integer range 8 to 32;
FAMILY: integER range 0 to 21); port (CLK: in STD_Logic;
RESETN: in STD_Logic;
WEN: in sTD_LOGIC;
addr: in std_logic_VECTOR(7 downto 0);
WD: in STD_Logic_vectOR(DWIDth-1 downto 0);
RD: out std_loGIC_VECtor(dwidth-1 downto 0));
end ABCli0i;

architecture rtl of ABClI0I is

subtype ABCI10 is std_logIC_VECTor(DWIDTh-1 downto 0);

type ABCl1ii is array (integER range <> ) of ABCI10;

signal ABCii0i: std_logiC_VECTOr(15 downto 0);

signal ABCo00I: sTD_LOGIC_vector(15 downto 0);

signal ABCl00i: STD_logic_veCTOR(15 downto 0);

signal ABCi00I: std_LOGIC_vector(15 downto 0);

signal ABCo10i: STD_logic;

signal ABCIo1: std_loGIC;

signal ABCol1: std_LOGIC;

begin
ABCIO1 <= '0';
ABCol1 <= '1';
ABCO10I <= not WEn;
ABCL10i:
if FAMILY = 0
generate
process (CLK)
variable RAM: ABCL1ii(0 to 255);
variable ABCi10i: std_logic_VECTOR(7 downto 0);
variable ABCI1ii: integer range 0 to 255 := 0;
begin
if CLK'evENT and CLK = '1' then
ABCi10i := ( others => '0');
for ABCll in 0 to 7
loop
if ADDR(ABCll) = '1' then
ABCI10I(ABCll) := '1';
end if;
end loop;
ABCi1ii := CONV_INTeger(ABCi10i);
if WEN = '1' then
RAM(ABCi1ii) := wd;
end if;
rd <= RAM(ABCi1ii);
end if;
end process;
end generate;
ABCOO1i:
if FAMILY = 11 or FAMILY = 12
generate
ABClo1i:
if DWidth = 8 or DWIDTH = 16
generate
ABCoI1: RAM256x16
port map (RWCLk => clk,
RESET => RESETN,
wen => WEN,
ren => ABCO10I,
WADDR => ADdr,
RADDR => ADDR,
wd => ABCii0i,
RD => ABCO00I);
end generate;
ABCIO1I:
if DWIDTH = 8
generate
ABCii0i <= "00000000"&wd;
RD <= ABCo00i(7 downto 0);
end generate;
ABCOL1I:
if dwidth = 16
generate
ABCii0I <= wd;
rd <= ABCo00i;
end generate;
ABCLL1i:
if DWIDth = 32
generate
ABCil1I: ram256X16
port map (rwclk => CLK,
Reset => RESETN,
WEN => Wen,
ren => ABCo10I,
waddR => ADDR,
RAddr => addr,
wd => WD(15 downto 0),
rd => rd(15 downto 0));
ABCoi1i: ram256x16
port map (RWCLK => CLK,
Reset => RESETN,
WEN => WEN,
ren => ABCo10i,
WADDr => ADDR,
raddr => ADDr,
wd => WD(31 downto 16),
rd => rd(31 downto 16));
end generate;
end generate;
ABCli1i:
if FAMILY = 14
generate
ABCoi1:
for ABCll in 0 to DWIDth/8-1
generate
ABCoi1: ram256x8
port map (rwcLK => CLK,
reset => clk,
WEN => WEN,
REn => ABCol1,
WADDR => ADDR,
raddr => Addr,
wd => wd(ABCll*8+7 downto ABCll*8),
RD => rd(ABCLL*8+7 downto ABCLL*8));
end generate;
end generate;
ABCIi1i:
if FAMILY = 15 or FAMILY = 16
or FAMILY = 17
generate
ABCOI1: ram256X16
port map (rwclk => clK,
rESET => RESETN,
WEN => WEN,
ren => ABCo10i,
WADDr => Addr,
RADDR => aDDR,
WD => ABCIi0i,
rD => ABCo00i);
ABCio1i:
if DWidth = 8
generate
ABCii0i <= "00000000"&wD;
RD <= ABCo00i(7 downto 0);
end generate;
ABCol1i:
if DWidth = 16
generate
ABCii0i <= WD;
RD <= ABCo00i;
end generate;
ABCO01i:
if Dwidth = 32
generate
ABCl01i: ram256x16
port map (RWCLK => clk,
RESET => RESETN,
WEN => WEN,
ren => ABCo10i,
Waddr => adDR,
RADdr => ADdr,
wd => ABCl00i,
RD => ABCI00i);
ABCii0i <= WD(15 downto 0);
ABCL00I <= wd(31 downto 16);
rD <= ABCI00I&ABCO00I;
end generate;
end generate;
end rtl;