-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library Ieee;
use ieee.STD_logIC_1164.all;
use ieee.STD_Logic_aritH.all;
use ieee.std_lOGIC_UNsigned.all;
library FUSION;
use fusION.COMPONENts.all;
use WOrk.supPORT.all;
entity ABCi01 is
generic (AWIdth: INTeger range 1 to 16;
DWidth: inTEGER range 8 to 32;
SWIdth: integeR range 0 to 4;
ICWIDTH: INTEGER range 1 to 16;
ABCoi0: inteGER range 1 to 65536;
IWWIDth: integeR range 1 to 64;
ID: INTEGER range 0 to 25); port (CLK: in std_loGIC;
ABCLI0: in STD_LOGIc;
ABCO11: in std_LOGIC;
ABCL11: out Std_logic;
address: in STd_logic_vECTOR(ICWIDTH-1 downto 0);
instRUCTION: out std_LOGIC_Vector(Iwwidth-1 downto 0));
end ABCI01;

architecture Rtl of ABCi01 is

constant ABCO0i: Integer := AWIDTH;

constant ABCl0I: integer := DWIDth;

constant ABCi0I: integer := max(swidth,
1);

constant ABCo1i: INTEGer := ICWIDTH;

constant ABCi11: INteger := ABCO0I+ABCl0i+ABCi0i+6;

signal ABCoool: STD_LOGIc_vector(19 downto 0);

signal ABClool: std_loGIC_VECtor(31 downto 0);

signal ABCIOOL: STD_logic_vectOR(1 downto 0);

signal ABColol: std_logic;

signal ABCLLOl: STD_Logic;

signal ABCIlol: stD_LOGIC;

signal ABCoiol: STD_LOgic;

signal ABCLIOL: std_logIC;

signal ABCIIOL: std_logic;

signal ABCO0OL: std_logiC;

signal ABCl0ol: std_LOGIC;

signal ABCI0OL: STd_logic;

signal ABCo1OL: STD_logic;

signal ABCL1Ol: std_logic;

signal ABCi1ol: std_loGIC;

signal ABCooll: std_loGIC;

signal ABCloll: std_LOGIC;

signal ABCioLL: std_LOGIC;

signal ABCOLLL: std_logIC_VECTor(31 downto 0);

signal ABCllll: std_logic;

signal ABCilll: std_loGIC_VECtor(1 downto 0);

signal ABCOIll: STd_logic;

signal ABClill: STD_logic;

signal ABCiill: STd_logic;

signal ABCO0LL: std_LOGIC;

signal ABCl10: STD_Logic_vectOR(63 downto 0);

signal ABCl0lL: STD_logic_vecTOR(63 downto 0);

signal ABCio1: STD_Logic;

signal ABCOL1: STd_logic;

-- synthesis translate_off
constant ABCi0lL: STRING(1 to 12) := "NVMABC_"&charACTER'vaL(Id+48)&".mem";

-- synthesis translate_on
begin
ABCIO1 <= '0';
ABCOL1 <= '1';
ABCOILL <= ABCo11;
process (Clk,ABCli0)
begin
if ABCli0 = '0' then
ABCLILL <= '0';
ABCIILL <= '0';
ABCO0ll <= '0';
elsif CLK'EVent and CLK = '1' then
ABClill <= ABCoill and ABCll1(ABCI11 > 32);
if ABCOill = '1' then
ABCiiLL <= '1';
elsif ABCLlll = '0' then
ABCiill <= '0';
end if;
ABCo0ll <= ABCIILl and ABCLL1(ABCi11 > 32);
end if;
end process;
process (ADDRESS,ABCoill)
begin
ABCoool <= ( others => '0');
if ABCI11 > 32 then
ABCOOOL(ICWIDTH-1+3 downto 0) <= address(ICWIDTH-1 downto 0)&not ABCoill&"00";
else
ABCOOol(ICWIDTH-1+2 downto 0) <= address(ICWIDTH-1 downto 0)&"00";
end if;
end process;
ABCOLOl <= ABCOILL or ABCiilL
or ABCo0ll;
ABCl11 <= ABCLLLL or (ABCiill and ABCll1(ABCi11 > 32));
ABCL0OL <= '0';
ABCiool <= "10";
ABCLIOL <= '0';
ABCiioL <= '0';
ABCioll <= '0';
ABCo1oL <= '0';
ABCi1oL <= '0';
ABCilol <= '0';
ABCooll <= '0';
ABCloll <= '0';
ABCiiol <= '0';
ABCO0OL <= '0';
ABCi0oL <= '0';
ABClool <= ( others => '0');
ABCOIOL <= '0';
ABCL1OL <= '0';
ABCLLOL <= '0';
ABCo1ll: nvm
-- synthesis translate_off
generic map (memoryfile => ABCI0ll)
-- synthesis translate_on
port map (ADDR => ABCoool(17 downto 0),
wD => ABClooL,
datawidth => ABCIOOL,
ren => ABColol,
Readnext => ABClloL,
pagestatuS => ABCILOl,
wen => ABCoiol,
ERASEPage => ABCliol,
PROGram => ABCIiol,
sparEPAGE => ABCo0ol,
AUXBLOCK => ABCL0ol,
UNPROTEctpage => ABCI0ol,
OVERWRItepage => ABCO1ol,
diSCARDPAGe => ABCl1ol,
OVERWRITEprotect => ABCi1ol,
PagelossprOTECT => ABCoOLL,
piPE => ABCLOLl,
lockrequEST => ABCIOLL,
clk => clk,
RESET => ABCli0,
RD => ABColll,
BUSY => ABCLLLL,
STATUS => ABCILLL);
process (cLK)
begin
if clk'EVEnt and clk = '1' then
if ABCIill = '1' then
ABCL0Ll(31 downto 0) <= ABColll;
end if;
if ABCo0ll = '1' then
ABCl0ll(63 downto 32) <= ABColll;
end if;
end if;
end process;
process (ABCiill,ABCo0lL,ABColll,ABCl0LL)
begin
if ABCi11 <= 32 then
if ABCiILL = '1' then
ABCl10(31 downto 0) <= ABCOLLL;
else
ABCL10(31 downto 0) <= ABCl0LL(31 downto 0);
end if;
ABCl10(63 downto 32) <= ( others => '-');
else
ABCl10(31 downto 0) <= ABCl0lL(31 downto 0);
if ABCO0LL = '1' then
ABCl10(63 downto 32) <= ABColll;
else
ABCl10(63 downto 32) <= ABCL0LL(63 downto 32);
end if;
end if;
end process;
process (ABCl10)
begin
INSTRUCtion <= ( others => '-');
instructioN(5 downto 0) <= ABCL10(5 downto 0);
if ABCi0i > 0 then
iNSTRUCTIon(ABCi0i-1+6 downto 6) <= ABCl10(ABCi0i-1+6 downto 6);
end if;
iNSTRUCTIOn(ABCO0i-1+4+6 downto 4+6) <= ABCl10(ABCO0I-1+ABCI0I+6 downto ABCI0i+6);
INSTruction(ABCL0I-1+16+4+6 downto 16+4+6) <= ABCL10(ABCl0i-1+ABCo0i+ABCI0I+6 downto ABCO0I+ABCI0I+6);
end process;
end rtl;