-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library ieee;
use ieee.Std_logiC_1164.all;
use ieee.Std_logic_aRITH.all;
use ieeE.STD_LOGic_unsignED.all;
use Work.SUPPORT.all;
-- synthesis translate_off
use WORk.TEXTIO.all;
-- synthesis translate_on
entity DEBUGBLK is
generic (debUG: INTEGER range 0 to 1;
Awidth: integER range 1 to 16;
dwidTH: Integer range 8 to 32;
SWIDTH: integer range 0 to 4;
sdepth: INTEGER range 1 to 16;
ICWIDTH: integer range 1 to 16;
ICDEpth: INTeger range 1 to 65536;
zrwidtH: INTEger range 0 to 16;
iiwidth: inteGER range 1 to 32;
iowiDTH: INTEGEr range 1 to 32;
irWIDTH: INTEGer range 1 to 32;
EN_mult: inteGER range 0 to 3); port (pclk: in std_logiC;
rESETN: in std_lOGIC;
Isr: in std_logiC;
SMADdr: in sTD_LOGIC_vector(ICWIDTH-1 downto 0);
instr_CMD: in std_loGIC_VECTor(2 downto 0);
Instr_scmd: in Std_logic_vECTOR(2 downto 0);
instr_DATA: in std_logic_VECTOR(DWIDTh-1 downto 0);
instr_ADDR: in STD_LOgic_vectoR(AWIdth-1 downto 0);
INSTR_slot: in STD_LOgic_vectoR(swIDTH downto 0);
PRDATA: in STD_logic_vectOR(dwidth-1 downto 0);
PWDATA: in Std_logic_vECTOR(DWIDth-1 downto 0);
accum_olD: in std_LOGIC_Vector(Dwidth-1 downto 0);
Accum_new: in STD_logic_vecTOR(dwidTH-1 downto 0);
ACcum_zero: in STD_LOGic;
ACCUM_neg: in std_logic;
FLags: in STD_Logic;
ramdoUT: in STd_logic_veCTOR(dwidth-1 downto 0);
Stkptr: in std_logic_VECTOR(7 downto 0);
ZREGister: in STd_logic_veCTOR(ZRWIDTH downto 0);
Acmdo: in std_LOGIC;
debug1: in std_logic;
DEbug2: in STD_logic);
end DEBUGBLK;

architecture RTL of DEBUGBLK is

-- synthesis translate_off
function ABCi(X: std_LOGIC_VEctor;
B: STD_logic)
return INTEGER is
variable ABCol: integER;
begin
for ABCll in x'range
loop
if X(ABCLL) = b then
ABCol := ABClL;
end if;
end loop;
return (ABCOL);
end ABCI;

function ABCil(ABCoi,ABClI: Std_logic_vECTOR;
ABCii: integeR range 0 to 7;
ABCo0: std_LOGIC_Vector;
ABCL0: std_logiC;
addr: STD_Logic_vectOR)
return sTRING is
variable ABCi0: STd_logic_veCTOR(2 downto 0);
variable ABCo1: strinG(1 to 80);
variable ABCl1: integeR;
begin
case ABCo0(1 downto 0) is
when "00" =>
ABCl1 := 0;
when "01" =>
ABCl1 := 1;
when "10" =>
ABCl1 := 14;
when others =>
ABCl1 := 15;
end case;
if ABCL0 /= '1' then
case ABCii is
when 0 =>
if EN_MULT = 0 then
SPRIntf(ABCo1,
"ACCUM %02x <= %02x INC",
fmt(ABCoI)&fmt(ABCLI));
else
sprINTF(ABCO1,
"ACCUM %02x <= %02x MULT %02x",
fmT(ABCoi)&FMT(ABCLI)&fmT(ABCo0));
end if;
when 1 =>
Sprintf(ABCo1,
"ACCUM %02x <= %02x AND %02x",
fMT(ABCoi)&fmt(ABCli)&fmt(ABCo0));
when 2 =>
SPrintf(ABCo1,
"ACCUM %02x <= %02x OR  %02x",
FMT(ABCoi)&FMT(ABCLi)&FMT(ABCo0));
when 3 =>
sprintF(ABCo1,
"ACCUM %02x <= %02x XOR %02x",
fmt(ABCoi)&Fmt(ABCLI)&FMT(ABCO0));
when 4 =>
Sprintf(ABCO1,
"ACCUM %02x <= %02x ADD %02x",
fmt(ABCoi)&fmt(ABCLI)&fmt(ABCo0));
when 5 =>
if ABCL1 = 15 then
sprintf(ABCO1,
"ACCUM %02x <= %02x ROL",
fmt(ABCoi)&FMT(ABCLI));
else
SPRintf(ABCO1,
"ACCUM %02x <= %02x SHL%x",
FMT(ABCOI)&fmt(ABCli)&fmt(ABCl1));
end if;
when 6 =>
if ABCL1 = 15 then
SPrintf(ABCo1,
"ACCUM %02x <= %02x ROR",
FMT(ABCOI)&fmt(ABCLI));
else
sprintf(ABCo1,
"ACCUM %02x <= %02x SHR%x",
fmt(ABCoi)&FMT(ABCli)&fmt(ABCl1));
end if;
when 7 =>
SPrintf(ABCo1,
"LOAD %02x",
fMT(ABCo0));
when others =>
SPRINTF(ABCo1,
"UNEXPECTED INSTRUCTION");
end case;
else
case ABCii is
when 0 =>
if EN_MULT > 0 then
SPRINTF(ABCo1,
"ACCUM %02x <= %02x MULT RAM(%d) %02x",
fMT(ABCOI)&FMT(ABClI)&FMT(ADdr)&fmt(ABCO0));
end if;
when 1 =>
SPRINTF(ABCO1,
"ACCUM %02x <= %02x AND RAM(%d) %02x",
fmt(ABCoi)&fmT(ABCli)&FMT(addr)&fmt(ABCO0));
when 2 =>
SPRintf(ABCo1,
"ACCUM %02x <= %02x OR  RAM(%d) %02x",
FMT(ABCoi)&fmt(ABCLI)&fmt(addr)&fmT(ABCo0));
when 3 =>
sprintf(ABCo1,
"ACCUM %02x <= %02x XOR RAM(%d) %02x",
fmt(ABCoi)&fMT(ABCLI)&FMt(aDDR)&FMT(ABCo0));
when 4 =>
sprintf(ABCO1,
"ACCUM %02x <= %02x ADD RAM(%d) %02x",
FMT(ABCoi)&FMT(ABCli)&fmt(ADDR)&FMT(ABCo0));
when 7 =>
sprintf(ABCO1,
"LOAD RAM(%d) %02x",
fmt(addr)&fmt(ABCo0));
when others =>
sprintf(ABCo1,
"UNEXPECTED INSTRUCTION");
end case;
end if;
return (ABCO1);
end ABCIL;

function ABCI1(ABCOI,ABCLI: std_logiC_VECTOr;
ABCIi: Integer range 0 to 7;
ABCo0: stD_LOGIC_vector;
ABCl0: std_LOGIC;
addr: Std_logic_vECTOR)
return stRING is
variable ABCi0: STd_logic_vECTOR(2 downto 0);
variable ABCO1: strinG(1 to 16);
variable ABCL1: intEGER;
begin
if ABCl0 /= '1' then
case ABCii is
when 1 =>
SPRintf(ABCo1,
"BITTST (%02x) %d",
FMT(ABCLI)&FMt(ABCi(ABCO0,
'1')));
when 3 =>
sprintf(ABCO1,
"CMP (%02x) to %02x",
fmt(ABCli)&FMT(ABCo0));
when 4 =>
SPRIntf(ABCO1,
"CMPLEQ (%02x) %02x",
FMT(ABCLi)&FMT(ABCo0));
when others =>
SPRINTF(ABCo1,
"UNEXPECTED INSTRUCTION");
end case;
else
case ABCII is
when 3 =>
sprintF(ABCo1,
"CMP (%02x) RAM(%d) %02x",
fmt(ABCLI)&FMT(addr)&fmt(ABCO0));
when others =>
SPRintf(ABCo1,
"UNEXPECTED INSTRUCTION");
end case;
end if;
return (ABCO1);
end ABCI1;

function ABCool(ABCLOL,ABCIi: std_logIC_VECTor;
IIWIDTH: integER)
return stRING is
variable ABCO1: string(1 to 80);
begin
if ABCLOL(0) = '1' then
if ABCII(0) = '1' then
Sprintf(ABCo1,
"ALWAYS");
else
SPRIntf(ABCO1,
"NEVER");
end if;
else
sprINTF(ABCO1,
"");
if ABCII(0) = '0' then
sprintf(ABCO1,
"NOTIF");
else
spriNTF(ABCO1,
"IF");
end if;
if ABCLOL(1) = '1' then
Sprintf(ABCO1,
"%s ZERO",
fmt(ABCo1));
end if;
if ABClol(2) = '1' then
sprinTF(ABCo1,
"%s NEG",
fmt(ABCo1));
end if;
if ABClol(3) = '1' then
sprintf(ABCO1,
"%s LCZERO",
fmT(ABCo1));
end if;
for ABCll in 0 to min(IIWIDTH,
ABCloL'LEFT+1-4)-1
loop
if ABCloL(4+ABCll) = '1' then
sprINTF(ABCO1,
"%s INPUT%d",
fmt(ABCo1)&FMT(ABCLL));
end if;
end loop;
end if;
return (ABCo1);
end ABCool;

function ABCiol(ACC: stD_LOGIC_vector)
return STring is
variable ABCO1: STRing(1 to 4);
begin
if ACC = 0 then
ABCo1 := "ZERO";
elsif ACC(DWIDTH-1) = '1' then
ABCO1 := "NEG ";
else
ABCo1 := "POS ";
end if;
return (ABCO1);
end ABCiol;

function ABColl(flags: std_LOGIC;
ABCO0: STD_LOGic_vector)
return STRING is
variable ABCo1: striNG(1 to 4);
begin
if ABCo0(0) = '1' then
return (" ");
elsif flags = '1' then
return (" (taken)");
else
return (" (not taken)");
end if;
end ABCOLL;

function ABCLLl(ABCoi,ABCli: std_logic_VECTOR;
ABCILL,ABCoil,ABCLIL,addr,ABCo0,sTKPTR,Zregister: std_logIC_VECTor;
ABCIil: integer;
acmdo: std_logIC;
FLAGS: STD_LOGic)
return STRing is
variable ABCO0L,ABCII: integer range 0 to 7;
variable ABCo1: string(1 to 40);
variable ABCL0: std_LOGIC;
variable ABCL0l: std_logiC_VECTOr(ABCo0'range );
variable ABCi0l,ABCO1l: sTD_LOGIC_vector(ABCO0'range );
begin
ABCi0l := ( others => '0');
ABCi0l(0) := '1';
ABCO1l := ( others => '1');
ABCl0l := 0-clean(ABCo0);
ABCO0l := 0;
ABCii := 0;
ABCl0 := ABCLIL(0);
for ABClL in 0 to 2
loop
if ABCIll(ABCll) = '1' then
ABCo0l := ABCo0L+2**ABCLL;
end if;
if ABCoil(ABCll) = '1' then
ABCII := ABCii+2**ABCLL;
end if;
end loop;
case ABCO0l is
when 0 =>
SPRINTF(ABCO1,
"%s",
fmt(ABCil(ABCoi,
ABCli,
ABCII,
ABCo0,
ABCl0,
ADdr)));
when 1 =>
sprintf(ABCO1,
"%s",
fMT(ABCi1(ABCoi,
ABCLI,
ABCII,
ABCO0,
ABCl0,
ADdr)));
when 2 =>
case ABCiI is
when 0 =>
SPRintf(ABCo1,
"APBWRT ACC %d:%02x = %02x",
FMT(ABClIL)&fmt(addr)&FMT(ABCO0));
when 1 =>
sprintf(ABCo1,
"APBWRT DAT %d:%02x = %02x",
FMT(ABClil)&fmt(addr)&fmt(ABCo0));
when 2 =>
if ACMDO = '1' then
sprintf(ABCO1,
"APBWRT ACM %d:%02x = %02x",
FMt(ABClIL)&FMT(addr)&fmt(ABCo0(7 downto 0)));
else
SPrintf(ABCO1,
"APBWRT ACM %d:%02x (No Write)",
FMT(ABCLIL)&fmT(ADDR));
end if;
when 3 =>
sprintf(ABCo1,
"APBREAD %d:%02x = %02x",
fmT(ABClil)&fmt(ADDR)&Fmt(ABCo0));
when 4 =>
SPRintf(ABCo1,
"APBWRTZ ACC %d:Z(%02x) = %02x",
Fmt(ABClIL)&FMT(ZREGISTer)&fmt(ABCo0));
when 5 =>
spRINTF(ABCO1,
"APBWRTZ DAT %d:Z(%02x) = %02x",
fmt(ABCLIL)&fmt(zregiSTER)&FMT(ABCo0));
when 6 =>
if acmdo = '1' then
SPRINTF(ABCo1,
"APBWRTZ ACM %d:Z(%02x) = %02x",
fMT(ABClil)&FMT(ZREGISTEr)&fmt(ABCo0(7 downto 0)));
else
SPRINtf(ABCO1,
"APBWRTZ ACM %d:Z(%02x) (No Write)",
FMT(ABClil)&fMT(Zregister));
end if;
when 7 =>
sprinTF(ABCo1,
"APBREADZ %d:Z(%02x) = %02x",
FMT(ABClil)&fmt(zregisTER)&fmt(ABCO0));
when others =>
sprintf(ABCO1,
"UNEXPECTED INSTRUCTION");
end case;
when 3 =>
case ABCII is
when 0 =>
if ABCl0 /= '1' then
SPRINTF(ABCO1,
"LOADZ DAT %02x",
FMt(ABCO0));
else
SPRINtf(ABCo1,
"LOADZ ACC %02x",
fmt(ABClI));
end if;
when 1 =>
if ABCl0 = '0' then
if ABCo0 = ABCI0L then
spriNTF(ABCO1,
"INCZ <= %02x +1 ",
fMT(zregister));
elsif ABCO0 = ABCO1L then
SPRINtf(ABCo1,
"DECZ <= %02x -1",
fmT(ZREGIster));
elsif ABCo0(ABCo0'left) = '0' then
SPRINTF(ABCo1,
"ADDZ <= %02x + %02x",
fmT(ZREGIster)&fmt(ABCo0));
else
sprintf(ABCo1,
"SUBZ <= %02x - %02x",
fmt(Zregister)&fmt(ABCL0l));
end if;
else
sPRINTF(ABCO1,
"ADDZ <= %02x + ACC(%02x)",
fmT(ZRegister)&fmt(ABCli));
end if;
when 6 =>
sprintf(ABCO1,
"IOREAD %02x ",
FMT(ABCoi));
when 7 =>
if ABCl0 /= '1' then
sprintf(ABCo1,
"IOWRT DAT %02x ",
fmt(ABCO0));
else
sprintf(ABCo1,
"IOWRT ACC %02x ",
FMT(ABCLI));
end if;
when 3 =>
SPrintf(ABCO1,
"RAMREAD %02x = %02x",
FMT(ADDR)&FMT(ABCoi));
when 2 =>
if ABCl0 /= '1' then
SPRINtf(ABCo1,
"RAMWRITE DAT %02x = %02x",
FMT(addr)&fmt(ABCO0));
else
sprintf(ABCo1,
"RAMWRITE ACC %02x = %02x",
FMT(ADDR)&FMT(ABCO0));
end if;
when 4 =>
if ABCL0 /= '1' then
sprintf(ABCo1,
"PUSH DAT %02x (SP=%02x)",
FMt(ABCo0)&FMT(stKPTR));
else
SPrintf(ABCo1,
"PUSH ACC %02x (SP=%02x)",
fmt(ABCLI)&fmt(stkPTR));
end if;
when 5 =>
sprintF(ABCo1,
"POP  %02x (SP=%02x)",
FMT(ABCOI)&fmt(STKptr));
when others =>
spRINTF(ABCo1,
"UNEXPECTED INSTRUCTION");
end case;
when 4 =>
if ABCOIL(1) = '0' then
SPRINTF(ABCo1,
"JUMP %s %d %s",
fmt(ABCOOL(ABCo0,
ABCoil,
IIWIDTH))&fmt(addr)&FMT(ABColl(FLags,
ABCo0)));
else
SPrintf(ABCO1,
"WAIT %s %s",
fmt(ABCool(ABCO0,
ABCoiL,
IIWIDTH))&fmT(ABColl(FLAGS,
ABCO0)));
end if;
when 5 =>
SPRINTf(ABCO1,
"CALL %s %d %s (SP=%02x)",
fmt(ABCool(ABCO0,
ABCOIL,
IIWIDTH))&Fmt(ADDR)&fmt(ABColl(Flags,
ABCo0))&fMT(STKptr));
when 6 =>
if ABCoil(1) = '0' then
sprintf(ABCo1,
"RETURN %s  %s (SP=%02x)",
fmt(ABCool(ABCO0,
ABCOIL,
IIWIDTH))&fmt(ABCOll(flags,
ABCo0))&fmt(stkPTR));
else
SPRIntf(ABCo1,
"RETISR %s  %s (SP=%02x)",
fmt(ABCOOL(ABCo0,
ABCoiL,
IIWIDTH))&fmt(ABCOLl(flAGS,
ABCO0))&FMT(stkptr));
end if;
when 7 =>
sPRINTF(ABCo1,
"NOP");
when others =>
sprINTF(ABCo1,
"NOT DONE");
end case;
return (ABCO1);
end ABCLLL;

function ABCl1L(ABCILL,ABCoil,ABCi1l: Std_logic_vECTOR)
return integer is
variable ABCo0L,ABCII: INteger range 0 to 7;
variable ABCooi: INTEGER;
begin
ABCo0l := 0;
ABCII := 0;
for ABCLL in 0 to 2
loop
if ABCILL(ABCLL) = '1' then
ABCo0L := ABCo0l+2**ABCLL;
end if;
if ABCOil(ABClL) = '1' then
ABCii := ABCII+2**ABCll;
end if;
end loop;
ABCooi := 1;
case ABCO0l is
when 0 =>
if ABCi1L(0) = '1' then
ABCooi := 3;
end if;
when 1 =>
if ABCi1l(0) = '1' then
ABCooi := 3;
end if;
when 2 =>
if ABCii = 2 or ABCii = 6 then
ABCooi := 4;
elsif ABCii = 3 or ABCii = 7 then
ABCOOI := 2;
end if;
when 3 =>
if ABCiI = 3 or ABCii = 5 then
ABCOOI := 3;
end if;
when others =>
end case;
return (ABCOOi);
end ABCl1l;

function ABCloi(ABCo0: stD_LOGIC_vector)
return STD_LOGIc_vector is
variable ABCIOI: sTD_LOGIC_vector(ABCO0'range );
begin
ABCIOI := ( others => '0');
for ABCll in ABCioi'range
loop
if ABCO0(ABCll) = '1' then
ABCIOI(ABCll) := '1';
end if;
end loop;
return (ABCioi);
end ABCloi;

signal ABColi: STD_logic_veCTOR(7 downto 0);

signal ABClli: sTD_LOGIC_vector(7 downto 0);

signal ABCILi: STD_LOgic;

-- synthesis translate_on
begin
-- synthesis translate_off
ABColI <= clean(STKPTr)-1;
ABClli <= CLEAn(STKPTR)+1;
process
begin
wait for 1 ns;
printf("# INFO CoreABC VHDL 2.3 Disassembler");
wait;
end process;
process (PCLK)
variable ABCoi: sTD_LOGIC_vector(dwidth-1 downto 0);
variable ABCLI: Std_logic_vECTOR(DWIdth-1 downto 0);
variable ABCoii: Std_logic := '0';
variable ABClII: std_loGIC := '0';
variable addr: STD_logic_vectOR(AWIDth-1 downto 0);
variable ABCO0: std_lOGIC_VEctor(DWIDTH-1 downto 0);
variable ABCiii: STD_LOgic;
variable ABCooi: iNTEGER;
begin
if PCLK'EVENT and PCLK = '1'
and DEBUG = 1
and RESETN = '1' then
ABCili <= DEBUg1;
ABCoi := ACCUM_new;
ABCLI := accUM_OLD;
ABCoii := ABClii;
ABClii := isr;
ABCIII := INSTR_slot(0);
if INSTR_Cmd(2 downto 1) = "00" and ABCiii = '1' then
ABCO0 := ABCLOI(RAMDOUt);
else
ABCO0 := ABCloi(INSTR_DAta);
end if;
ADDR := ABCLOI(INSTR_addr);
if ABClii = '1' and ABCOII = '0' then
printf("Entering ISR: (SP=%02x)",
fmt(stKPTR));
end if;
if ABClii = '0' and ABCoii = '1' then
printf("Exiting ISR: (SP=%02x)",
FMT(stkptR));
end if;
ABCooi := ABCL1L(INSTr_cmd,
insTR_SCMD,
instr_SLOT);
if dEBUG1 = '1' then
if ABCooi = 1 then
PRIntf("INS:%d: %s",
fmt(SMADdr)&Fmt(ABClll(ABCoi,
ABCli,
INSTr_cmd,
instR_SCMD,
instr_slot,
ADDR,
ABCO0,
stkptr,
ZREGISTEr,
IIWIDTH,
acmdo,
flags)));
end if;
end if;
if ABCILI = '1' then
if ABCooi = 3 then
PRINTF("INS:%d: %s",
FMT(smaDDR)&FMT(ABCllL(ABCoi,
ABCli,
Instr_cmd,
instr_SCMD,
INSTr_slot,
addr,
ABCo0,
STKPtr,
ZREGISter,
IIWIDTH,
ACMDO,
FLAGS)));
end if;
if ABCooi = 4 then
PRINTf("INS:%d: %s",
fMT(Smaddr)&FMT(ABClLL(ABCoI,
ABCli,
instR_CMD,
instr_scmD,
INSTR_SLot,
ADDR,
PWDATA,
STKPTR,
ZREGISter,
IIWIDTH,
aCMDO,
FLAGS)));
end if;
end if;
if debug2 = '1' then
if ABCoOI = 2 then
PRIntf("INS:%d: %s",
Fmt(SMaddr)&fmt(ABClll(ABCOI,
ABCli,
inSTR_CMD,
INSTR_scmd,
INStr_slot,
ADDR,
PRDATA,
STKPTR,
ZREGIster,
IIWIDTH,
ACMdo,
flags)));
end if;
end if;
end if;
end process;
-- synthesis translate_on
end rTL;