-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library Ieee;
use IEEE.std_logic_1164.all;
use ieee.STD_logic_arITH.all;
use ieEE.sTD_LOGIC_unsigneD.all;
use WORK.suppoRT.all;
entity ABCiL0 is
generic (Awidth: INteger range 1 to 16;
DWIDTH: integer range 8 to 32;
swidth: integER range 0 to 4;
ICWIDTH: integer range 1 to 16;
ABCoi0: intEGER range 1 to 65536;
iwwiDTH: INTEGer range 1 to 64;
INITWIDTH: integer range 1 to 16;
TESTMODE: INTEGER range 0 to 99;
ID: INTEGEr range 0 to 25); port (CLK: in STD_logic;
ABCli0: in std_lOGIC;
INitdatval: in stD_LOGIC;
INITdone: in Std_logic;
INITADDR: in STD_logic_vecTOR(INITWIDTH-1 downto 0);
INITDATA: in STD_Logic_vectOR(8 downto 0);
ADdress: in std_logic_VECTOR(ICWIDTH-1 downto 0);
Instruction: out std_logic_VECTOR(Iwwidth-1 downto 0));
end ABCil0;

architecture rtl of ABCIL0 is

constant ABCo0i: Integer := aWIDTH;

constant ABCl0i: INteger := dwidth;

constant ABCi0i: integer := max(SWIDTH,
1);

constant ABCo1i: Integer := ICWIDTH;

constant ABCii0: integer := 2**ICWIDTH;

constant ABCo00: INTEger := ABCO0I+ABCl0i+ABCi0I+6;

constant ABCl00: INTEGER := 1+(ABCII0-1)/512;

constant ABCI00: integer := 1+(ABCo00-1)/9;

signal ABCo10: STD_LOGic_vectoR(15 downto 0);

signal ABCl10: std_lOGIC_VECtor(9*ABCi00-1 downto 0);

subtype ABCi10 is STD_logic_vecTOR(9*ABCi00-1 downto 0);

type ABCoo1 is array (INTEGer range 0 to ABCl00-1) of ABCI10;

signal RDATAX: ABCoo1;

signal RENABle: std_lOGIC;

signal WENABLe: std_logiC_VECTOr(ABCL00*ABCi00-1 downto 0);

signal ABCLo1: stD_LOGIC_vector(63 downto 0);

signal ABCIO1: std_logic;

signal ABCOl1: std_loGIC;

begin
ABCio1 <= '0';
ABCOL1 <= '1';
process (INITADDR)
begin
ABClo1 <= ( others => '0');
for c in 0 to ABCI00-1
loop
for R in 0 to ABCl00-1
loop
ABCLO1(R*ABCi00+c) <= ABClL1(INITADDR(INITWIDTH-1 downto 9) = r*ABCi00+C);
end loop;
end loop;
end process;
RENABLE <= initdONE;
process (addresS)
begin
ABCO10 <= ( others => '0');
ABCo10(ICWIDTH-1 downto 0) <= Address;
end process;
ABCil1:
for c in 0 to ABCi00-1
generate
ABCOI1:
for R in 0 to ABCl00-1
generate
wenaBLE(r*ABCi00+C) <= not inITDone and ABClo1(r*ABCI00+c)
and INITDATVal;
ABCLI1: iram512X9
generic map (ID => Id,
rid => r,
CID => c)
port map (rd => rdataX(r)(c*9+8 downto C*9),
RADDr => ABCO10(8 downto 0),
RWCLK => Clk,
reset => ABCli0,
wenable => WENABLE(r*ABCI00+C),
renable => renable,
INITaddr => INITADDR(8 downto 0),
iniTDATA => INITDATA);
end generate;
end generate;
ABCii1:
if ABCl00 = 1
generate
ABCl10 <= rdatax(0);
end generate;
ABCo01:
if ABCl00 > 1
generate
process (Rdatax,addRESS)
variable ABCl01: inTEGER range 0 to ABCl00-1;
begin
ABCl01 := CONV_integer(addrESS(ICWIDTH-1 downto 9));
ABCl10 <= rDATAX(ABCl01);
end process;
end generate;
process (ABCL10)
begin
inSTRUCTIOn <= ( others => '-');
InstructioN(5 downto 0) <= ABCL10(5 downto 0);
if ABCi0i > 0 then
instructION(ABCi0i-1+6 downto 6) <= ABCl10(ABCi0i-1+6 downto 6);
end if;
instrucTION(ABCO0I-1+4+6 downto 4+6) <= ABCL10(ABCo0i-1+ABCI0i+6 downto ABCi0i+6);
instructioN(ABCl0i-1+16+4+6 downto 16+4+6) <= ABCL10(ABCL0i-1+ABCO0I+ABCi0i+6 downto ABCo0I+ABCI0I+6);
end process;
end rtl;