?? testbench.vhd
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-- ********************************************************************/
-- Copyright 2007 Actel Corporation. All rights reserved.
-- IP Engineering
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- File: testbench.vhd
--
-- Description: Simple APB Bus Controller
-- Testbench
--
-- Rev: 2.3 01Mar07 IPB : Production Release
--
-- Notes:
--
-- *********************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.support.all;
use work.misc.all;
use work.textio.all;
use work.testsupport.all;
use work.components.all;
use work.coreparameters.all;
entity TESTBENCH is
generic ( SET_FAMILY : integer range -1 to 21 := -1; -- force family setting
SET_DEBUG : integer range -1 to 1 := -1; -- force debug off/on
SET_TM : integer range -1 to 99 := -1; -- force test instruction set
SET_PROG : integer range 0 to 5 := 0 -- Core Program Mode
);
end TESTBENCH;
--SET_PROG
-- 0: core operates as set up
-- 1: core forced to HARD mode
-- 2: core forced to HARD mode and RAM Image generated
-- 3: core forced to SOFT mode, initialisation by RAM models loading
-- 4: core forced to SOFT mode, initialisation from INITCFG interface
-- 5: core forced to NVM mode
architecture TEST of TESTBENCH is
constant FAMILYX : integer range 0 to 21 := override(SET_FAMILY,FAMILY);
constant DEBUGX : integer range 0 to 1 := override(SET_DEBUG,DEBUG);
constant TESTMODEX : integer range 0 to 99 := override(SET_TM,11); -- By default testbench runs tests 11
constant INSMODEX : integer range 0 to 2 := overrideP(SET_PROG,INSMODE);
constant ENABLE_HEXFILE : boolean := ( SET_PROG=2);
constant ENABLE_INIT : boolean := ( SET_PROG=4);
-- When TESTMODE=0 the core parameters are extracted from coreparameters.vhd
-- >0 then the core parameters are taken from the testsupport package using TESTMODE
-- to select the settings
constant APBsetupX : TABCCONFIG := APBsetup(TESTMODEX,FAMILYX,INSMODEX);
constant PARA_ID : integer := set_generic(TESTMODEX,ID ,APBsetupX.ID);
constant PARA_FAMILY : integer := set_generic(TESTMODEX,FAMILYX ,APBsetupX.FAMILY);
constant PARA_APB_AWIDTH : integer := set_generic(TESTMODEX,APB_AWIDTH ,APBsetupX.APB_AWIDTH);
constant PARA_APB_DWIDTH : integer := set_generic(TESTMODEX,APB_DWIDTH ,APBsetupX.APB_DWIDTH);
constant PARA_APB_SDEPTH : integer := set_generic(TESTMODEX,APB_SDEPTH ,APBsetupX.APB_SDEPTH);
constant PARA_ICWIDTH : integer := set_generic(TESTMODEX,ICWIDTH ,APBsetupX.ICWIDTH);
constant PARA_ZRWIDTH : integer := set_generic(TESTMODEX,ZRWIDTH ,APBsetupX.ZRWIDTH);
constant PARA_IIWIDTH : integer := set_generic(TESTMODEX,IIWIDTH ,APBsetupX.IIWIDTH);
constant PARA_IFWIDTH : integer := set_generic(TESTMODEX,IFWIDTH ,APBsetupX.IFWIDTH);
constant PARA_IOWIDTH : integer := set_generic(TESTMODEX,IOWIDTH ,APBsetupX.IOWIDTH);
constant PARA_STWIDTH : integer := set_generic(TESTMODEX,STWIDTH ,APBsetupX.STWIDTH);
constant PARA_EN_INC : integer := set_generic(TESTMODEX,EN_INC ,APBsetupX.EN_INC);
constant PARA_EN_ADD : integer := set_generic(TESTMODEX,EN_ADD ,APBsetupX.EN_ADD);
constant PARA_EN_AND : integer := set_generic(TESTMODEX,EN_AND ,APBsetupX.EN_AND);
constant PARA_EN_OR : integer := set_generic(TESTMODEX,EN_OR ,APBsetupX.EN_OR);
constant PARA_EN_XOR : integer := set_generic(TESTMODEX,EN_XOR ,APBsetupX.EN_XOR);
constant PARA_EN_SHL : integer := set_generic(TESTMODEX,EN_SHL ,APBsetupX.EN_SHL);
constant PARA_EN_SHR : integer := set_generic(TESTMODEX,EN_SHR ,APBsetupX.EN_SHR);
constant PARA_EN_CALL : integer := set_generic(TESTMODEX,EN_CALL ,APBsetupX.EN_CALL);
constant PARA_EN_RAM : integer := set_generic(TESTMODEX,EN_RAM ,APBsetupX.EN_RAM);
constant PARA_EN_ACM : integer := set_generic(TESTMODEX,EN_ACM ,APBsetupX.EN_ACM);
constant PARA_EN_MULT : integer := set_generic(TESTMODEX,EN_MULT ,APBsetupX.EN_MULT);
constant PARA_EN_PUSH : integer := set_generic(TESTMODEX,EN_PUSH ,APBsetupX.EN_PUSH);
constant PARA_EN_DATAM : integer := set_generic(TESTMODEX,EN_DATAM ,APBsetupX.EN_DATAM);
constant PARA_INITWIDTH : integer := set_generic(TESTMODEX,INITWIDTH ,APBsetupX.INITWIDTH);
constant PARA_EN_INT : integer := set_generic(TESTMODEX,EN_INT ,APBsetupX.EN_INT);
constant PARA_EN_IOREAD : integer := set_generic(TESTMODEX,EN_IOREAD ,APBsetupX.EN_IOREAD );
constant PARA_EN_IOWRT : integer := set_generic(TESTMODEX,EN_IOWRT ,APBsetupX.EN_IOWRT );
constant PARA_EN_ALURAM : integer := set_generic(TESTMODEX,EN_ALURAM ,APBsetupX.EN_ALURAM);
constant PARA_ISRADDR : integer := set_generic(TESTMODEX,ISRADDR ,APBsetupX.ISRADDR);
constant PARA_TESTMODE : integer := set_generic(TESTMODEX,TESTMODEX ,APBsetupX.TESTMODE);
constant PARA_DEBUG : integer := DEBUGX;
constant PARA_INSMODE : integer := set_generic(TESTMODEX,INSMODEX ,APBsetupX.INSMODE);
constant PARA_EN_INDIRECT : integer := set_generic(TESTMODEX,EN_INDIRECT ,APBsetupX.EN_INDIRECT);
type PDATA_ARRAY is array ( INTEGER range <>) of std_logic_vector(PARA_APB_DWIDTH-1 downto 0);
signal PRDATA : PDATA_ARRAY(0 to 15);
signal STATUSSTR : STRING(1 to 4);
signal FINISHED : BOOLEAN := FALSE;
signal STOPCLK : BOOLEAN := FALSE;
signal CYCLES : INTEGER;
signal PCLK : std_logic;
signal PRESETN : std_logic;
signal PENABLE : std_logic;
signal PWRITE : std_logic;
signal PSEL : std_logic_vector( 15 downto 0);
signal PADDR : std_logic_vector( PARA_APB_AWIDTH-1 downto 0);
signal PWDATA : std_logic_vector( PARA_APB_DWIDTH-1 downto 0);
signal PRDATAMUX : std_logic_vector( PARA_APB_DWIDTH-1 downto 0);
signal PREADY : std_logic;
signal IO_IN : std_logic_vector( PARA_IIWIDTH-1 downto 0);
signal IO_OUT : std_logic_vector( PARA_IOWIDTH-1 downto 0);
signal INITDATVAL : std_logic;
signal INITDONE : std_logic;
signal INITADDR : std_logic_vector(PARA_INITWIDTH-1 downto 0);
signal INITDATA : std_logic_vector(8 downto 0);
signal INTREQ : std_logic;
signal INTACT : std_logic;
signal IOSWITCH : std_logic;
signal IOWAITIN : std_logic;
constant ZERO : std_logic_vector(31 downto 0) := ( others => '0');
constant ONES : std_logic_vector(31 downto 0) := ( others => '1');
begin
--------------------------------------------------------------------------------
-- Hex File Generation
UHEX: MAKEHEX
generic map ( ENABLE => ENABLE_HEXFILE,
ID => PARA_ID,
FAMILY => PARA_FAMILY,
AWIDTH => PARA_APB_AWIDTH,
DWIDTH => PARA_APB_DWIDTH,
SDEPTH => PARA_APB_SDEPTH,
ICWIDTH => PARA_ICWIDTH,
IIWIDTH => PARA_IIWIDTH,
IFWIDTH => PARA_IFWIDTH,
TESTMODE => PARA_TESTMODE
);
------------------------------------------------------------------------------
-- Model the INITCFG Block loading the RAM
--
UCFG: INITGEN
generic map( ENABLE => ENABLE_INIT,
ID => PARA_ID,
AWIDTH => PARA_APB_AWIDTH,
DWIDTH => PARA_APB_DWIDTH,
SDEPTH => PARA_APB_SDEPTH,
ICWIDTH => PARA_ICWIDTH,
INITWIDTH => PARA_INITWIDTH
)
port map ( PCLK => PCLK,
PRESETN => PRESETN,
INITDATVAL => INITDATVAL,
INITDONE => INITDONE,
INITADDR => INITADDR,
INITDATA => INITDATA
);
--------------------------------------------------------------------------------
-- Clock Generation
process
begin
PCLK <= '0';
wait for 31250 ps;
PCLK <= '1';
wait for 31250 ps;
if STOPCLK then
wait;
end if;
end process;
--------------------------------------------------------------------------------
-- The ABC Core
UUT : COREABC
generic map ( ID => PARA_ID,
FAMILY => PARA_FAMILY,
APB_AWIDTH => PARA_APB_AWIDTH,
APB_DWIDTH => PARA_APB_DWIDTH,
APB_SDEPTH => PARA_APB_SDEPTH,
ICWIDTH => PARA_ICWIDTH,
ZRWIDTH => PARA_ZRWIDTH,
IIWIDTH => PARA_IIWIDTH,
IFWIDTH => PARA_IFWIDTH,
IOWIDTH => PARA_IOWIDTH,
STWIDTH => PARA_STWIDTH,
ISRADDR => PARA_ISRADDR,
EN_INT => PARA_EN_INT,
EN_RAM => PARA_EN_RAM,
EN_INC => PARA_EN_INC,
EN_ADD => PARA_EN_ADD,
EN_AND => PARA_EN_AND,
EN_OR => PARA_EN_OR,
EN_XOR => PARA_EN_XOR,
EN_SHL => PARA_EN_SHL,
EN_SHR => PARA_EN_SHR,
EN_CALL => PARA_EN_CALL,
EN_PUSH => PARA_EN_PUSH,
EN_MULT => PARA_EN_MULT,
EN_ACM => PARA_EN_ACM,
EN_DATAM => PARA_EN_DATAM,
EN_IOREAD => PARA_EN_IOREAD,
EN_IOWRT => PARA_EN_IOWRT,
EN_ALURAM => PARA_EN_ALURAM,
EN_INDIRECT => PARA_EN_INDIRECT,
DEBUG => PARA_DEBUG,
INSMODE => PARA_INSMODE,
INITWIDTH => PARA_INITWIDTH,
TESTMODE => PARA_TESTMODE
)
port map ( NSYSRESET => PRESETN,
PCLK => PCLK,
PRESETN => open,
PENABLE => PENABLE,
PWRITE => PWRITE,
PSEL => PSEL(PARA_APB_SDEPTH-1 downto 0),
PADDR => PADDR,
PWDATA => PWDATA,
PRDATA => PRDATAMUX,
PREADY => PREADY,
IO_IN => IO_IN,
IO_OUT => IO_OUT,
INTREQ => INTREQ,
INTACT => INTACT,
INITDATVAL => INITDATVAL,
INITDONE => INITDONE,
INITADDR => INITADDR,
INITDATA => INITDATA
);
------------------------------------------------------------------------------
-- APB Bus Mux
--
PSEL <= ( others => 'L'); -- force PSEL bus to weak pull downs, Core only outputs enough bits
process(PSEL,PRDATA)
variable msel : std_logic_vector(3 downto 0);
variable mint : integer range 0 to 15;
begin
msel(0) := PSEL(1) or PSEL(3) or PSEL(5) or PSEL(7) or PSEL(9) or PSEL(11) or PSEL(13) or PSEL(15);
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