Fitter report for dds
Fri May 08 23:20:40 2009
Quartus II Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Partition Preservation Settings
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Delay Chain Summary
 14. Pad To Core Delay Chain Fanout
 15. Control Signals
 16. Global & Other Fast Signals
 17. Non-Global High Fan-Out Signals
 18. Fitter RAM Summary
 19. Interconnect Usage Summary
 20. LAB Logic Elements
 21. LAB-wide Signals
 22. LAB Signals Sourced
 23. LAB Signals Sourced Out
 24. LAB Distinct Inputs
 25. Fitter Device Options
 26. Operating Settings and Conditions
 27. Advanced Data - General
 28. Advanced Data - Placement Preparation
 29. Advanced Data - Placement
 30. Advanced Data - Routing
 31. Fitter Messages
 32. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Fri May 08 23:20:40 2009         ;
; Quartus II Version                 ; 8.0 Build 231 07/10/2008 SP 1 SJ Full Version ;
; Revision Name                      ; dds                                           ;
; Top-level Entity Name              ; dds                                           ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C5Q208C8                                   ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 69 / 4,608 ( 1 % )                            ;
;     Total combinational functions  ; 68 / 4,608 ( 1 % )                            ;
;     Dedicated logic registers      ; 69 / 4,608 ( 1 % )                            ;
; Total registers                    ; 69                                            ;
; Total pins                         ; 38 / 142 ( 27 % )                             ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 6,656 / 119,808 ( 6 % )                       ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                                ;
; Total PLLs                         ; 0 / 2 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                      ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                             ; Setting                        ; Default Value                  ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                             ; EP2C5Q208C8                    ;                                ;
; Fit Attempts to Skip                                               ; 0                              ; 0.0                            ;
; Device I/O Standard                                                ; 3.3-V LVTTL                    ;                                ;
; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;