?? prev_cmp_dds.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 08 23:20:44 2009 " "Info: Processing started: Fri May 08 23:20:44 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off dds -c dds " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dds -c dds" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 08 23:20:46 2009 " "Info: Processing ended: Fri May 08 23:20:46 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 08 23:20:47 2009 " "Info: Processing started: Fri May 08 23:20:47 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off dds -c dds --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dds -c dds --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SYSCLK " "Info: Assuming node \"SYSCLK\" is an undefined clock" { } { { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "SYSCLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SYSCLK memory altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0 register SIN_OUT\[6\]~reg0 170.71 MHz 5.858 ns Internal " "Info: Clock \"SYSCLK\" has Internal fmax of 170.71 MHz between source memory \"altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0\" and destination register \"SIN_OUT\[6\]~reg0\" (period= 5.858 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.544 ns + Longest memory register " "Info: + Longest memory to register delay is 5.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X11_Y10 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y10; Fanout = 9; MEM Node = 'altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5h11.tdf" "" { Text "D:/中期成果/dds/db/altsyncram_5h11.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.761 ns) 3.761 ns altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|q_a\[6\] 2 MEM M4K_X11_Y10 1 " "Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X11_Y10; Fanout = 1; MEM Node = 'altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|q_a\[6\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_5h11.tdf" "" { Text "D:/中期成果/dds/db/altsyncram_5h11.tdf" 31 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.469 ns) + CELL(0.206 ns) 5.436 ns temp_sin~123 3 COMB LCCOMB_X17_Y10_N18 1 " "Info: 3: + IC(1.469 ns) + CELL(0.206 ns) = 5.436 ns; Loc. = LCCOMB_X17_Y10_N18; Fanout = 1; COMB Node = 'temp_sin~123'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.675 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] temp_sin~123 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 171 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.544 ns SIN_OUT\[6\]~reg0 4 REG LCFF_X17_Y10_N19 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 5.544 ns; Loc. = LCFF_X17_Y10_N19; Fanout = 1; REG Node = 'SIN_OUT\[6\]~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { temp_sin~123 SIN_OUT[6]~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 173 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.075 ns ( 73.50 % ) " "Info: Total cell delay = 4.075 ns ( 73.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.469 ns ( 26.50 % ) " "Info: Total interconnect delay = 1.469 ns ( 26.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.544 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] temp_sin~123 SIN_OUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.544 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] {} temp_sin~123 {} SIN_OUT[6]~reg0 {} } { 0.000ns 0.000ns 1.469ns 0.000ns } { 0.000ns 3.761ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.094 ns - Smallest " "Info: - Smallest clock skew is -0.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.793 ns + Shortest register " "Info: + Shortest clock path from clock \"SYSCLK\" to destination register is 2.793 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns SYSCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'SYSCLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYSCLK } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns SYSCLK~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'SYSCLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { SYSCLK SYSCLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 2.793 ns SIN_OUT\[6\]~reg0 3 REG LCFF_X17_Y10_N19 1 " "Info: 3: + IC(0.844 ns) + CELL(0.666 ns) = 2.793 ns; Loc. = LCFF_X17_Y10_N19; Fanout = 1; REG Node = 'SIN_OUT\[6\]~reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { SYSCLK~clkctrl SIN_OUT[6]~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 173 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.66 % ) " "Info: Total cell delay = 1.806 ns ( 64.66 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.987 ns ( 35.34 % ) " "Info: Total interconnect delay = 0.987 ns ( 35.34 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { SYSCLK SYSCLK~clkctrl SIN_OUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} SIN_OUT[6]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 2.887 ns - Longest memory " "Info: - Longest clock path from clock \"SYSCLK\" to source memory is 2.887 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns SYSCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'SYSCLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYSCLK } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns SYSCLK~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'SYSCLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { SYSCLK SYSCLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.769 ns) + CELL(0.835 ns) 2.887 ns altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M4K_X11_Y10 9 " "Info: 3: + IC(0.769 ns) + CELL(0.835 ns) = 2.887 ns; Loc. = M4K_X11_Y10; Fanout = 9; MEM Node = 'altsyncram:sin_rom\|altsyncram_5h11:auto_generated\|ram_block1a0~porta_address_reg0'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { SYSCLK~clkctrl altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5h11.tdf" "" { Text "D:/中期成果/dds/db/altsyncram_5h11.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns ( 68.41 % ) " "Info: Total cell delay = 1.975 ns ( 68.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.912 ns ( 31.59 % ) " "Info: Total interconnect delay = 0.912 ns ( 31.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.887 ns" { SYSCLK SYSCLK~clkctrl altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.887 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.143ns 0.769ns } { 0.000ns 1.140ns 0.000ns 0.835ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { SYSCLK SYSCLK~clkctrl SIN_OUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} SIN_OUT[6]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.887 ns" { SYSCLK SYSCLK~clkctrl altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.887 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.143ns 0.769ns } { 0.000ns 1.140ns 0.000ns 0.835ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" { } { { "db/altsyncram_5h11.tdf" "" { Text "D:/中期成果/dds/db/altsyncram_5h11.tdf" 34 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 173 0 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.544 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] temp_sin~123 SIN_OUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.544 ns" { altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:sin_rom|altsyncram_5h11:auto_generated|q_a[6] {} temp_sin~123 {} SIN_OUT[6]~reg0 {} } { 0.000ns 0.000ns 1.469ns 0.000ns } { 0.000ns 3.761ns 0.206ns 0.108ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.793 ns" { SYSCLK SYSCLK~clkctrl SIN_OUT[6]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.793 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} SIN_OUT[6]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.844ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.887 ns" { SYSCLK SYSCLK~clkctrl altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.887 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.143ns 0.769ns } { 0.000ns 1.140ns 0.000ns 0.835ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sync_fcw\[4\] FCW\[4\] SYSCLK 6.321 ns register " "Info: tsu for register \"sync_fcw\[4\]\" (data pin = \"FCW\[4\]\", clock pin = \"SYSCLK\") is 6.321 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.163 ns + Longest pin register " "Info: + Longest pin to register delay is 9.163 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns FCW\[4\] 1 PIN PIN_203 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_203; Fanout = 1; PIN Node = 'FCW\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCW[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.456 ns) + CELL(0.615 ns) 9.055 ns sync_fcw~295 2 COMB LCCOMB_X13_Y11_N8 1 " "Info: 2: + IC(7.456 ns) + CELL(0.615 ns) = 9.055 ns; Loc. = LCCOMB_X13_Y11_N8; Fanout = 1; COMB Node = 'sync_fcw~295'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.071 ns" { FCW[4] sync_fcw~295 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.163 ns sync_fcw\[4\] 3 REG LCFF_X13_Y11_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 9.163 ns; Loc. = LCFF_X13_Y11_N9; Fanout = 2; REG Node = 'sync_fcw\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sync_fcw~295 sync_fcw[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 102 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.707 ns ( 18.63 % ) " "Info: Total cell delay = 1.707 ns ( 18.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.456 ns ( 81.37 % ) " "Info: Total interconnect delay = 7.456 ns ( 81.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.163 ns" { FCW[4] sync_fcw~295 sync_fcw[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.163 ns" { FCW[4] {} FCW[4]~combout {} sync_fcw~295 {} sync_fcw[4] {} } { 0.000ns 0.000ns 7.456ns 0.000ns } { 0.000ns 0.984ns 0.615ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 102 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.802 ns - Shortest register " "Info: - Shortest clock path from clock \"SYSCLK\" to destination register is 2.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns SYSCLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'SYSCLK'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYSCLK } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns SYSCLK~clkctrl 2 COMB CLKCTRL_G2 87 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 87; COMB Node = 'SYSCLK~clkctrl'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { SYSCLK SYSCLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.666 ns) 2.802 ns sync_fcw\[4\] 3 REG LCFF_X13_Y11_N9 2 " "Info: 3: + IC(0.853 ns) + CELL(0.666 ns) = 2.802 ns; Loc. = LCFF_X13_Y11_N9; Fanout = 2; REG Node = 'sync_fcw\[4\]'" { } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.519 ns" { SYSCLK~clkctrl sync_fcw[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/中期成果/dds/dds.vhd" 102 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.45 % ) " "Info: Total cell delay = 1.806 ns ( 64.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 35.55 % ) " "Info: Total interconnect delay = 0.996 ns ( 35.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { SYSCLK SYSCLK~clkctrl sync_fcw[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} sync_fcw[4] {} } { 0.000ns 0.000ns 0.143ns 0.853ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.163 ns" { FCW[4] sync_fcw~295 sync_fcw[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.163 ns" { FCW[4] {} FCW[4]~combout {} sync_fcw~295 {} sync_fcw[4] {} } { 0.000ns 0.000ns 7.456ns 0.000ns } { 0.000ns 0.984ns 0.615ns 0.108ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { SYSCLK SYSCLK~clkctrl sync_fcw[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} sync_fcw[4] {} } { 0.000ns 0.000ns 0.143ns 0.853ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYSCLK SIN_OUT\[9\] SIN_OUT\[9\]~reg0 9.082 ns register " "Info: tco from clock \"SYSCLK\" to destination pin \"SIN_OUT\[9\]\" through register \"SIN_OUT\[9\]~reg0\" is 9.082 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 2.793 ns + Longest regist?? 快捷鍵說明
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