--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 BYTEENA_ACLR_A="NONE" BYTEENA_ACLR_B="NONE" BYTEENA_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_CORE_A="USE_INPUT_CLKEN" CLOCK_ENABLE_CORE_B="USE_INPUT_CLKEN" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CLOCK_ENABLE_OUTPUT_A="NORMAL" CLOCK_ENABLE_OUTPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" ENABLE_ECC="FALSE" IMPLEMENT_IN_LES="OFF" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INDATA_REG_B="CLOCK1" INIT_FILE_LAYOUT="PORT_A" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=0 NUMWORDS_B=0 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK1" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" read_during_write_mode_port_a="NEW_DATA_NO_NBE_READ" read_during_write_mode_port_b="NEW_DATA_NO_NBE_READ" WIDTH_A=37 WIDTH_B=37 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=11 WIDTHAD_B=11 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 8.0SP1 cbx_altsyncram 2008:06:16:296212 cbx_cycloneii 2008:06:02:292401 cbx_lpm_add_sub 2008:06:02:292401 cbx_lpm_compare 2008:06:02:292401 cbx_lpm_decode 2008:06:02:292401 cbx_lpm_mux 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratix 2008:06:02:292401 cbx_stratixii 2008:06:02:292401 cbx_stratixiii 2008:06:18:296807 cbx_util_mgl 2008:06:02:292401  VERSION_END


-- Copyright (C) 1991-2008 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION altsyncram_0hq1 (address_a[10..0], address_b[10..0], clock0, clock1, clocken0, clocken1, data_a[36..0], data_b[36..0], wren_a, wren_b)
RETURNS ( q_a[36..0], q_b[36..0]);

--synthesis_resources = M4K 19 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_k7p3
( 
	address_a[10..0]	:	input;
	address_b[10..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken1	:	input;
	data_a[36..0]	:	input;
	q_b[36..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_0hq1;

BEGIN 
	altsyncram1.address_a[] = address_b[];
	altsyncram1.address_b[] = address_a[];
	altsyncram1.clock0 = clock1;
	altsyncram1.clock1 = clock0;
	altsyncram1.clocken0 = clocken1;
	altsyncram1.clocken1 = wren_a;
	altsyncram1.data_a[] = B"1111111111111111111111111111111111111";
	altsyncram1.data_b[] = data_a[];
	altsyncram1.wren_a = B"0";
	altsyncram1.wren_b = wren_a;
	q_b[] = altsyncram1.q_a[];
END;
--VALID FILE