--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" lpm_modulus=1 lpm_port_updown="PORT_CONNECTIVITY" lpm_width=1 clk_en clock q sclr CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 8.0SP1 cbx_cycloneii 2008:06:02:292401 cbx_lpm_add_sub 2008:06:02:292401 cbx_lpm_compare 2008:06:02:292401 cbx_lpm_counter 2008:06:02:292401 cbx_lpm_decode 2008:06:02:292401 cbx_mgl 2008:06:02:292401 cbx_stratix 2008:06:02:292401 cbx_stratixii 2008:06:02:292401  VERSION_END


-- Copyright (C) 1991-2008 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION cycloneii_lcell_comb (cin, dataa, datab, datac, datad)
WITH ( LUT_MASK, SUM_LUTC_INPUT)
RETURNS ( combout, cout);
FUNCTION cycloneii_lcell_ff (aclr, clk, datain, ena, sclr, sdata, sload)
WITH ( x_on_violation)
RETURNS ( regout);

--synthesis_resources = lut 2 reg 1 
SUBDESIGN cntr_gui
( 
	clk_en	:	input;
	clock	:	input;
	q[0..0]	:	output;
	sclr	:	input;
) 
VARIABLE 
	counter_comb_bita0 : cycloneii_lcell_comb
		WITH (
			LUT_MASK = "5A90",
			SUM_LUTC_INPUT = "cin"
		);
	counter_reg_bit1a[0..0] : cycloneii_lcell_ff;
	cmpr2_aeb_int	:	WIRE;
	cmpr2_aeb	:	WIRE;
	cmpr2_dataa[0..0]	:	WIRE;
	cmpr2_datab[0..0]	:	WIRE;
	aclr_actual	: WIRE;
	cnt_en	: NODE;
	compare_result	: WIRE;
	cout_actual	: WIRE;
	data[0..0]	: NODE;
	external_cin	: WIRE;
	modulus_bus[0..0]	: WIRE;
	modulus_trigger	: WIRE;
	s_val[0..0]	: WIRE;
	safe_q[0..0]	: WIRE;
	sload	: NODE;
	sset	: NODE;
	time_to_clear	: WIRE;
	updown_dir	: WIRE;

BEGIN 
	counter_comb_bita[0..0].cin = ( external_cin);
	counter_comb_bita[0..0].dataa = ( counter_reg_bit1a[0].regout);
	counter_comb_bita[0..0].datab = ( updown_dir);
	counter_comb_bita[0..0].datad = ( B"1");
	counter_reg_bit1a[].aclr = aclr_actual;
	counter_reg_bit1a[].clk = clock;
	counter_reg_bit1a[].datain = ( counter_comb_bita[0].combout);
	counter_reg_bit1a[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
	counter_reg_bit1a[].sdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & ((sload & data[]) # (((! sload) & modulus_bus[]) & (! updown_dir))))));
	counter_reg_bit1a[].sload = (((sclr # sset) # sload) # modulus_trigger);
	IF ((0,cmpr2_dataa[]) == (0,cmpr2_datab[])) THEN
		cmpr2_aeb_int = VCC;
	ELSE
		cmpr2_aeb_int = GND;
	END IF;
	cmpr2_aeb = cmpr2_aeb_int;
	cmpr2_dataa[] = safe_q[];
	cmpr2_datab[] = modulus_bus[];
	aclr_actual = B"0";
	cnt_en = VCC;
	compare_result = cmpr2_aeb;
	cout_actual = (counter_comb_bita[0].cout # (time_to_clear & updown_dir));
	data[] = GND;
	external_cin = B"1";
	modulus_bus[] = B"0";
	modulus_trigger = cout_actual;
	q[] = safe_q[];
	s_val[] = B"1";
	safe_q[] = counter_reg_bit1a[].regout;
	sload = GND;
	sset = GND;
	time_to_clear = compare_result;
	updown_dir = B"1";
END;
--VALID FILE