Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version
11
920
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
c:|altera|80|quartus|bin|megawizard_cache|
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
altsyncram
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|altsyncram.tdf
377de9a85d1ccfacb5bddd3c464c9087
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
13
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
9
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
512
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
sintable.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_m121
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
c:|altera|80|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
c:|altera|80|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
c:|altera|80|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
c:|altera|80|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
c:|altera|80|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
c:|altera|80|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
}
# macro_sequence

# end
# entity
altsyncram_m121
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# case_insensitive
# source_file
db|altsyncram_m121.tdf
4f93729d338ed4de789363ca8a665d0
6
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sintable.hex
4d192e960b1f41e248bd1b4d9d24018
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
37
PARAMETER_UNKNOWN
USR
sld_trigger_bits
37
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
35288
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
12260
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
256
PARAMETER_UNKNOWN
USR
sld_segment_size
256
PARAMETER_UNKNOWN
USR
SLD_RAM_BLOCK_TYPE
AUTO
PARAMETER_STRING
DEF
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
133
PARAMETER_UNKNOWN
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
37
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
37
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
35288
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
12260
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
256
PARAMETER_SIGNED_DEC
USR
sld_segment_size
256
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
133
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
 constraint(sld_ram_block_type)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 132
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(acq_data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
36 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
36 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_ela_control.vhd
ec28b7fa5b4dc0daa53c33c98b2921
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
37
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
8
PARAMETER_SIGNED_DEC
USR
sample_depth
256
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
current_resource_width
1
PARAMETER_SIGNED_DEC
USR
 constraint(advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(inversion_mask)
132 downto 132
PARAMETER_STRING
USR
 constraint(state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
 constraint(trigger_out_mode)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_resource_value)
0 downto 0
PARAMETER_STRING
USR
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
LPM_SHIFTREG
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|LPM_SHIFTREG.tdf
73c9c8ade8e954637797bb4bfbede563
6
# user_parameter {
LPM_WIDTH
4
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
}
# macro_sequence

# end
# entity
sld_ela_basic_multi_level_trigger
# storage
db|dds.(7).cnf
db|dds.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_ela_control.vhd
ec28b7fa5b4dc0daa53c33c98b2921
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
data_bits
37
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
 constraint(inversion_mask)
132 downto 132
PARAMETER_STRING
USR
 constraint(data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(trigger_level_match_out)
0 downto 0
PARAMETER_STRING
USR
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
b7ac8140a71dfdb7f372588a23bd
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f