|dds
SYSCLK => sync_fcw[21].CLK
SYSCLK => sync_fcw[20].CLK
SYSCLK => sync_fcw[19].CLK
SYSCLK => sync_fcw[18].CLK
SYSCLK => sync_fcw[17].CLK
SYSCLK => sync_fcw[16].CLK
SYSCLK => sync_fcw[15].CLK
SYSCLK => sync_fcw[14].CLK
SYSCLK => sync_fcw[13].CLK
SYSCLK => sync_fcw[12].CLK
SYSCLK => sync_fcw[11].CLK
SYSCLK => sync_fcw[10].CLK
SYSCLK => sync_fcw[9].CLK
SYSCLK => sync_fcw[8].CLK
SYSCLK => sync_fcw[7].CLK
SYSCLK => sync_fcw[6].CLK
SYSCLK => sync_fcw[5].CLK
SYSCLK => sync_fcw[4].CLK
SYSCLK => sync_fcw[3].CLK
SYSCLK => sync_fcw[2].CLK
SYSCLK => sync_fcw[1].CLK
SYSCLK => sync_fcw[0].CLK
SYSCLK => acc_adder[21].CLK
SYSCLK => acc_adder[20].CLK
SYSCLK => acc_adder[19].CLK
SYSCLK => acc_adder[18].CLK
SYSCLK => acc_adder[17].CLK
SYSCLK => acc_adder[16].CLK
SYSCLK => acc_adder[15].CLK
SYSCLK => acc_adder[14].CLK
SYSCLK => acc_adder[13].CLK
SYSCLK => acc_adder[12].CLK
SYSCLK => acc_adder[11].CLK
SYSCLK => acc_adder[10].CLK
SYSCLK => acc_adder[9].CLK
SYSCLK => acc_adder[8].CLK
SYSCLK => acc_adder[7].CLK
SYSCLK => acc_adder[6].CLK
SYSCLK => acc_adder[5].CLK
SYSCLK => acc_adder[4].CLK
SYSCLK => acc_adder[3].CLK
SYSCLK => acc_adder[2].CLK
SYSCLK => acc_adder[1].CLK
SYSCLK => acc_adder[0].CLK
SYSCLK => address[8].CLK
SYSCLK => address[7].CLK
SYSCLK => address[6].CLK
SYSCLK => address[5].CLK
SYSCLK => address[4].CLK
SYSCLK => address[3].CLK
SYSCLK => address[2].CLK
SYSCLK => address[1].CLK
SYSCLK => address[0].CLK
SYSCLK => sin_sign.CLK
SYSCLK => delay_sin_sign.CLK
SYSCLK => SIN_OUT[13]~reg0.CLK
SYSCLK => SIN_OUT[12]~reg0.CLK
SYSCLK => SIN_OUT[11]~reg0.CLK
SYSCLK => SIN_OUT[10]~reg0.CLK
SYSCLK => SIN_OUT[9]~reg0.CLK
SYSCLK => SIN_OUT[8]~reg0.CLK
SYSCLK => SIN_OUT[7]~reg0.CLK
SYSCLK => SIN_OUT[6]~reg0.CLK
SYSCLK => SIN_OUT[5]~reg0.CLK
SYSCLK => SIN_OUT[4]~reg0.CLK
SYSCLK => SIN_OUT[3]~reg0.CLK
SYSCLK => SIN_OUT[2]~reg0.CLK
SYSCLK => SIN_OUT[1]~reg0.CLK
SYSCLK => SIN_OUT[0]~reg0.CLK
SYSCLK => altsyncram:sin_rom.clock0
NCLR => delay_sin_sign~0.OUTPUTSELECT
NCLR => address~27.OUTPUTSELECT
NCLR => address~28.OUTPUTSELECT
NCLR => address~29.OUTPUTSELECT
NCLR => address~30.OUTPUTSELECT
NCLR => address~31.OUTPUTSELECT
NCLR => address~32.OUTPUTSELECT
NCLR => address~33.OUTPUTSELECT
NCLR => address~34.OUTPUTSELECT
NCLR => address~35.OUTPUTSELECT
NCLR => sin_sign~1.OUTPUTSELECT
NCLR => sync_fcw~0.OUTPUTSELECT
NCLR => sync_fcw~1.OUTPUTSELECT
NCLR => sync_fcw~2.OUTPUTSELECT
NCLR => sync_fcw~3.OUTPUTSELECT
NCLR => sync_fcw~4.OUTPUTSELECT
NCLR => sync_fcw~5.OUTPUTSELECT
NCLR => sync_fcw~6.OUTPUTSELECT
NCLR => sync_fcw~7.OUTPUTSELECT
NCLR => sync_fcw~8.OUTPUTSELECT
NCLR => sync_fcw~9.OUTPUTSELECT
NCLR => sync_fcw~10.OUTPUTSELECT
NCLR => sync_fcw~11.OUTPUTSELECT
NCLR => sync_fcw~12.OUTPUTSELECT
NCLR => sync_fcw~13.OUTPUTSELECT
NCLR => sync_fcw~14.OUTPUTSELECT
NCLR => sync_fcw~15.OUTPUTSELECT
NCLR => sync_fcw~16.OUTPUTSELECT
NCLR => sync_fcw~17.OUTPUTSELECT
NCLR => sync_fcw~18.OUTPUTSELECT
NCLR => sync_fcw~19.OUTPUTSELECT
NCLR => sync_fcw~20.OUTPUTSELECT
NCLR => sync_fcw~21.OUTPUTSELECT
NCLR => acc_adder~21.OUTPUTSELECT
NCLR => acc_adder~20.OUTPUTSELECT
NCLR => acc_adder~19.OUTPUTSELECT
NCLR => acc_adder~18.OUTPUTSELECT
NCLR => acc_adder~17.OUTPUTSELECT
NCLR => acc_adder~16.OUTPUTSELECT
NCLR => acc_adder~15.OUTPUTSELECT
NCLR => acc_adder~14.OUTPUTSELECT
NCLR => acc_adder~13.OUTPUTSELECT
NCLR => acc_adder~12.OUTPUTSELECT
NCLR => acc_adder~11.OUTPUTSELECT
NCLR => acc_adder~10.OUTPUTSELECT
NCLR => acc_adder~9.OUTPUTSELECT
NCLR => acc_adder~8.OUTPUTSELECT
NCLR => acc_adder~7.OUTPUTSELECT
NCLR => acc_adder~6.OUTPUTSELECT
NCLR => acc_adder~5.OUTPUTSELECT
NCLR => acc_adder~4.OUTPUTSELECT
NCLR => acc_adder~3.OUTPUTSELECT
NCLR => acc_adder~2.OUTPUTSELECT
NCLR => acc_adder~1.OUTPUTSELECT
NCLR => acc_adder~0.OUTPUTSELECT
FCW[0] => sync_fcw~21.DATAA
FCW[1] => sync_fcw~20.DATAA
FCW[2] => sync_fcw~19.DATAA
FCW[3] => sync_fcw~18.DATAA
FCW[4] => sync_fcw~17.DATAA
FCW[5] => sync_fcw~16.DATAA
FCW[6] => sync_fcw~15.DATAA
FCW[7] => sync_fcw~14.DATAA
FCW[8] => sync_fcw~13.DATAA
FCW[9] => sync_fcw~12.DATAA
FCW[10] => sync_fcw~11.DATAA
FCW[11] => sync_fcw~10.DATAA
FCW[12] => sync_fcw~9.DATAA
FCW[13] => sync_fcw~8.DATAA
FCW[14] => sync_fcw~7.DATAA
FCW[15] => sync_fcw~6.DATAA
FCW[16] => sync_fcw~5.DATAA
FCW[17] => sync_fcw~4.DATAA
FCW[18] => sync_fcw~3.DATAA
FCW[19] => sync_fcw~2.DATAA
FCW[20] => sync_fcw~1.DATAA
FCW[21] => sync_fcw~0.DATAA
SIN_OUT[0] <= SIN_OUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[1] <= SIN_OUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[2] <= SIN_OUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[3] <= SIN_OUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[4] <= SIN_OUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[5] <= SIN_OUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[6] <= SIN_OUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[7] <= SIN_OUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[8] <= SIN_OUT[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[9] <= SIN_OUT[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[10] <= SIN_OUT[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[11] <= SIN_OUT[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[12] <= SIN_OUT[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
SIN_OUT[13] <= SIN_OUT[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds|altsyncram:sin_rom
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5h11:auto_generated.address_a[0]
address_a[1] => altsyncram_5h11:auto_generated.address_a[1]
address_a[2] => altsyncram_5h11:auto_generated.address_a[2]
address_a[3] => altsyncram_5h11:auto_generated.address_a[3]
address_a[4] => altsyncram_5h11:auto_generated.address_a[4]
address_a[5] => altsyncram_5h11:auto_generated.address_a[5]
address_a[6] => altsyncram_5h11:auto_generated.address_a[6]
address_a[7] => altsyncram_5h11:auto_generated.address_a[7]
address_a[8] => altsyncram_5h11:auto_generated.address_a[8]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5h11:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5h11:auto_generated.q_a[0]
q_a[1] <= altsyncram_5h11:auto_generated.q_a[1]
q_a[2] <= altsyncram_5h11:auto_generated.q_a[2]
q_a[3] <= altsyncram_5h11:auto_generated.q_a[3]
q_a[4] <= altsyncram_5h11:auto_generated.q_a[4]
q_a[5] <= altsyncram_5h11:auto_generated.q_a[5]
q_a[6] <= altsyncram_5h11:auto_generated.q_a[6]
q_a[7] <= altsyncram_5h11:auto_generated.q_a[7]
q_a[8] <= altsyncram_5h11:auto_generated.q_a[8]
q_a[9] <= altsyncram_5h11:auto_generated.q_a[9]
q_a[10] <= altsyncram_5h11:auto_generated.q_a[10]
q_a[11] <= altsyncram_5h11:auto_generated.q_a[11]
q_a[12] <= altsyncram_5h11:auto_generated.q_a[12]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|dds|altsyncram:sin_rom|altsyncram_5h11:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT