/* * r2300.c: R2000 and R3000 specific mmu/cache code. * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * * with a lot of changes to make this thing work for R3000s * Tx39XX R4k style caches added. HK * Copyright (C) 1998, 1999, 2000 Harald Koerfgen * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov */#include <linux/init.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/mm.h>#include <asm/page.h>#include <asm/pgtable.h>#include <asm/mmu_context.h>#include <asm/system.h>#include <asm/isadep.h>#include <asm/io.h>#include <asm/wbflush.h>#include <asm/bootinfo.h>#include <asm/cpu.h>/* * According to the paper written by D. Miller about Linux cache & TLB * flush implementation, DMA/Driver coherence should be done at the  * driver layer.  Thus, normally, we don't need flush dcache for R3000. * Define this if driver does not handle cache consistency during DMA ops. *//* For R3000 cores with R4000 style caches */static unsigned long icache_size, dcache_size;		/* Size in bytes */static unsigned long icache_lsize, dcache_lsize;	/* Size in bytes */static unsigned long scache_size;#include <asm/cacheops.h>#include <asm/r4kcache.h>#undef DEBUG_TLB#undef DEBUG_CACHE/* page functions */void r3k_clear_page(void * page){	__asm__ __volatile__(		".set\tnoreorder\n\t"		".set\tnoat\n\t"		"addiu\t$1,%0,%2\n"		"1:\tsw\t$0,(%0)\n\t"		"sw\t$0,4(%0)\n\t"		"sw\t$0,8(%0)\n\t"		"sw\t$0,12(%0)\n\t"		"addiu\t%0,32\n\t"		"sw\t$0,-16(%0)\n\t"		"sw\t$0,-12(%0)\n\t"		"sw\t$0,-8(%0)\n\t"		"bne\t$1,%0,1b\n\t"		"sw\t$0,-4(%0)\n\t"		".set\tat\n\t"		".set\treorder"		:"=r" (page)		:"0" (page),		 "I" (PAGE_SIZE)		:"$1","memory");}static void r3k_copy_page(void * to, void * from){	unsigned long dummy1, dummy2;	unsigned long reg1, reg2, reg3, reg4;	__asm__ __volatile__(		".set\tnoreorder\n\t"		".set\tnoat\n\t"		"addiu\t$1,%0,%8\n"		"1:\tlw\t%2,(%1)\n\t"		"lw\t%3,4(%1)\n\t"		"lw\t%4,8(%1)\n\t"		"lw\t%5,12(%1)\n\t"		"sw\t%2,(%0)\n\t"		"sw\t%3,4(%0)\n\t"		"sw\t%4,8(%0)\n\t"		"sw\t%5,12(%0)\n\t"		"lw\t%2,16(%1)\n\t"		"lw\t%3,20(%1)\n\t"		"lw\t%4,24(%1)\n\t"		"lw\t%5,28(%1)\n\t"		"sw\t%2,16(%0)\n\t"		"sw\t%3,20(%0)\n\t"		"sw\t%4,24(%0)\n\t"		"sw\t%5,28(%0)\n\t"		"addiu\t%0,64\n\t"		"addiu\t%1,64\n\t"		"lw\t%2,-32(%1)\n\t"		"lw\t%3,-28(%1)\n\t"		"lw\t%4,-24(%1)\n\t"		"lw\t%5,-20(%1)\n\t"		"sw\t%2,-32(%0)\n\t"		"sw\t%3,-28(%0)\n\t"		"sw\t%4,-24(%0)\n\t"		"sw\t%5,-20(%0)\n\t"		"lw\t%2,-16(%1)\n\t"		"lw\t%3,-12(%1)\n\t"		"lw\t%4,-8(%1)\n\t"		"lw\t%5,-4(%1)\n\t"		"sw\t%2,-16(%0)\n\t"		"sw\t%3,-12(%0)\n\t"		"sw\t%4,-8(%0)\n\t"		"bne\t$1,%0,1b\n\t"		"sw\t%5,-4(%0)\n\t"		".set\tat\n\t"		".set\treorder"		:"=r" (dummy1), "=r" (dummy2),		 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)		:"0" (to), "1" (from),		 "I" (PAGE_SIZE));}unsigned long __init r3k_cache_size(unsigned long ca_flags){	unsigned long flags, status, dummy, size;	volatile unsigned long *p;	p = (volatile unsigned long *) KSEG0;	flags = read_32bit_cp0_register(CP0_STATUS);	/* isolate cache space */	write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC);	*p = 0xa5a55a5a;	dummy = *p;	status = read_32bit_cp0_register(CP0_STATUS);	if (dummy != 0xa5a55a5a || (status & ST0_CM)) {		size = 0;	} else {		for (size = 128; size <= 0x40000; size <<= 1)			*(p + size) = 0;		*p = -1;		for (size = 128; 		     (size <= 0x40000) && (*(p + size) == 0); 		     size <<= 1)			;		if (size > 0x40000)			size = 0;	}	write_32bit_cp0_register(CP0_STATUS, flags);	return size * sizeof(*p);}unsigned long __init r3k_cache_lsize(unsigned long ca_flags){	unsigned long flags, status, lsize, i, j;	volatile unsigned long *p;	p = (volatile unsigned long *) KSEG0;	flags = read_32bit_cp0_register(CP0_STATUS);	/* isolate cache space */	write_32bit_cp0_register(CP0_STATUS, (ca_flags|flags)&~ST0_IEC);	for (i = 0; i < 128; i++)		*(p + i) = 0;	*(volatile unsigned char *)p = 0;	for (lsize = 1; lsize < 128; lsize <<= 1) {		*(p + lsize);		status = read_32bit_cp0_register(CP0_STATUS);		if (!(status & ST0_CM))			break;	}	for (i = 0; i < 128; i += lsize)		*(volatile unsigned char *)(p + i) = 0;	write_32bit_cp0_register(CP0_STATUS, flags);	return lsize * sizeof(*p);}static void __init r3k_probe_cache(void){	dcache_size = r3k_cache_size(ST0_ISC);	if (dcache_size)		dcache_lsize = r3k_cache_lsize(ST0_ISC);		icache_size = r3k_cache_size(ST0_ISC|ST0_SWC);	if (icache_size)		icache_lsize = r3k_cache_lsize(ST0_ISC|ST0_SWC);}static void r3k_flush_icache_range(unsigned long start, unsigned long end){	unsigned long size, i, flags;	volatile unsigned char *p = (char *)start;	size = end - start;	if (size > icache_size)		size = icache_size;	flags = read_32bit_cp0_register(CP0_STATUS);	/* isolate cache space */	write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|ST0_SWC|flags)&~ST0_IEC);	for (i = 0; i < size; i += 0x080) {		asm ( 	"sb\t$0,0x000(%0)\n\t"			"sb\t$0,0x004(%0)\n\t"			"sb\t$0,0x008(%0)\n\t"			"sb\t$0,0x00c(%0)\n\t"			"sb\t$0,0x010(%0)\n\t"			"sb\t$0,0x014(%0)\n\t"			"sb\t$0,0x018(%0)\n\t"			"sb\t$0,0x01c(%0)\n\t"		 	"sb\t$0,0x020(%0)\n\t"			"sb\t$0,0x024(%0)\n\t"			"sb\t$0,0x028(%0)\n\t"			"sb\t$0,0x02c(%0)\n\t"			"sb\t$0,0x030(%0)\n\t"			"sb\t$0,0x034(%0)\n\t"			"sb\t$0,0x038(%0)\n\t"			"sb\t$0,0x03c(%0)\n\t"			"sb\t$0,0x040(%0)\n\t"			"sb\t$0,0x044(%0)\n\t"			"sb\t$0,0x048(%0)\n\t"			"sb\t$0,0x04c(%0)\n\t"			"sb\t$0,0x050(%0)\n\t"			"sb\t$0,0x054(%0)\n\t"			"sb\t$0,0x058(%0)\n\t"			"sb\t$0,0x05c(%0)\n\t"		 	"sb\t$0,0x060(%0)\n\t"			"sb\t$0,0x064(%0)\n\t"			"sb\t$0,0x068(%0)\n\t"			"sb\t$0,0x06c(%0)\n\t"			"sb\t$0,0x070(%0)\n\t"			"sb\t$0,0x074(%0)\n\t"			"sb\t$0,0x078(%0)\n\t"			"sb\t$0,0x07c(%0)\n\t"			: : "r" (p) );		p += 0x080;	}	write_32bit_cp0_register(CP0_STATUS,flags);}static void r3k_flush_dcache_range(unsigned long start, unsigned long end){	unsigned long size, i, flags;	volatile unsigned char *p = (char *)start;	size = end - start;	if (size > dcache_size)		size = dcache_size;	flags = read_32bit_cp0_register(CP0_STATUS);	/* isolate cache space */	write_32bit_cp0_register(CP0_STATUS, (ST0_ISC|flags)&~ST0_IEC);	for (i = 0; i < size; i += 0x080) {		asm ( 	"sb\t$0,0x000(%0)\n\t"			"sb\t$0,0x004(%0)\n\t"			"sb\t$0,0x008(%0)\n\t"			"sb\t$0,0x00c(%0)\n\t"		 	"sb\t$0,0x010(%0)\n\t"			"sb\t$0,0x014(%0)\n\t"			"sb\t$0,0x018(%0)\n\t"			"sb\t$0,0x01c(%0)\n\t"		 	"sb\t$0,0x020(%0)\n\t"			"sb\t$0,0x024(%0)\n\t"			"sb\t$0,0x028(%0)\n\t"			"sb\t$0,0x02c(%0)\n\t"		 	"sb\t$0,0x030(%0)\n\t"			"sb\t$0,0x034(%0)\n\t"			"sb\t$0,0x038(%0)\n\t"			"sb\t$0,0x03c(%0)\n\t"		 	"sb\t$0,0x040(%0)\n\t"			"sb\t$0,0x044(%0)\n\t"			"sb\t$0,0x048(%0)\n\t"			"sb\t$0,0x04c(%0)\n\t"		 	"sb\t$0,0x050(%0)\n\t"			"sb\t$0,0x054(%0)\n\t"			"sb\t$0,0x058(%0)\n\t"			"sb\t$0,0x05c(%0)\n\t"		 	"sb\t$0,0x060(%0)\n\t"			"sb\t$0,0x064(%0)\n\t"			"sb\t$0,0x068(%0)\n\t"			"sb\t$0,0x06c(%0)\n\t"		 	"sb\t$0,0x070(%0)\n\t"			"sb\t$0,0x074(%0)\n\t"			"sb\t$0,0x078(%0)\n\t"			"sb\t$0,0x07c(%0)\n\t"			: : "r" (p) );		p += 0x080;	}	write_32bit_cp0_register(CP0_STATUS,flags);}static inline unsigned long get_phys_page (unsigned long addr,					   struct mm_struct *mm){	pgd_t *pgd;	pmd_t *pmd;	pte_t *pte;	unsigned long physpage;	pgd = pgd_offset(mm, addr);	pmd = pmd_offset(pgd, addr);	pte = pte_offset(pmd, addr);	if ((physpage = pte_val(*pte)) & _PAGE_VALID)		return KSEG0ADDR(physpage & PAGE_MASK);	return 0;}static inline void r3k_flush_cache_all(void){	r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);} static void r3k_flush_cache_mm(struct mm_struct *mm){	if (mm->context != 0) {#ifdef DEBUG_CACHE		printk("cmm[%d]", (int)mm->context);#endif		r3k_flush_cache_all();	}}static void r3k_flush_cache_range(struct mm_struct *mm, unsigned long start,				  unsigned long end){	struct vm_area_struct *vma;	if (mm->context == 0) 		return;	start &= PAGE_MASK;#ifdef DEBUG_CACHE	printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);#endif	vma = find_vma(mm, start);	if (!vma)		return;	if (mm->context != current->active_mm->context) {		flush_cache_all();	} else {		unsigned long flags, physpage;		save_and_cli(flags);		while (start < end) {			if ((physpage = get_phys_page(start, mm)))				r3k_flush_icache_range(physpage,				                       physpage + PAGE_SIZE);			start += PAGE_SIZE;		}		restore_flags(flags);	}}static void r3k_flush_cache_page(struct vm_area_struct *vma,				   unsigned long page){	struct mm_struct *mm = vma->vm_mm;	if (mm->context == 0)		return;#ifdef DEBUG_CACHE	printk("cpage[%d,%08lx]", (int)mm->context, page);#endif	if (vma->vm_flags & VM_EXEC) {		unsigned long physpage;		if ((physpage = get_phys_page(page, vma->vm_mm)))			r3k_flush_icache_range(physpage, physpage + PAGE_SIZE);	}}static void r3k_flush_page_to_ram(struct page * page){	/*	 * Nothing to be done	 */}static void r3k_flush_icache_page(struct vm_area_struct *vma, struct page *page){	struct mm_struct *mm = vma->vm_mm;	unsigned long physpage;	if (mm->context == 0)		return;