/* *  linux/arch/arm/kernel/entry-armv.S * *  Copyright (C) 1996,1997,1998 Russell King. *  ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * *  Low-level vector interface routines * *  Note:  there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes *  it to save wrong values...  Be aware! */#include <linux/config.h>#include "entry-header.S"#ifdef IOC_BASE/* IOC / IOMD based hardware */#include <asm/hardware/iomd.h>		.equ	ioc_base_high, IOC_BASE & 0xff000000		.equ	ioc_base_low, IOC_BASE & 0x00ff0000		.macro	disable_fiq		mov	r12, #ioc_base_high		.if	ioc_base_low		orr	r12, r12, #ioc_base_low		.endif		strb	r12, [r12, #0x38]	@ Disable FIQ register		.endm		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		mov	r4, #ioc_base_high		@ point at IOC		.if	ioc_base_low		orr	r4, r4, #ioc_base_low		.endif		ldrb	\irqstat, [r4, #IOMD_IRQREQB]	@ get high priority first		ldr	\base, =irq_prio_h		teq	\irqstat, #0#ifdef IOMD_BASE		ldreqb	\irqstat, [r4, #IOMD_DMAREQ]	@ get dma		addeq	\base, \base, #256		@ irq_prio_h table size		teqeq	\irqstat, #0		bne	2406f#endif		ldreqb	\irqstat, [r4, #IOMD_IRQREQA]	@ get low priority		addeq	\base, \base, #256		@ irq_prio_d table size		teqeq	\irqstat, #0#ifdef IOMD_IRQREQC		ldreqb	\irqstat, [r4, #IOMD_IRQREQC]		addeq	\base, \base, #256		@ irq_prio_l table size		teqeq	\irqstat, #0#endif#ifdef IOMD_IRQREQD		ldreqb	\irqstat, [r4, #IOMD_IRQREQD]		addeq	\base, \base, #256		@ irq_prio_lc table size		teqeq	\irqstat, #0#endif2406:		ldrneb	\irqnr, [\base, \irqstat]	@ get IRQ number		.endm/* * Interrupt table (incorporates priority).  Please note that we * rely on the order of these tables (see above code). */		.macro	irq_prio_tableirq_prio_h:	.byte	 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10		.byte	12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10		.byte	14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10		.byte	15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10		.byte	15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10		.byte	13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10#ifdef IOMD_BASEirq_prio_d:	.byte	 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16		.byte	21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16#endifirq_prio_l:	.byte	 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3		.byte	 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3		.byte	 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5		.byte	 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5		.byte	 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3		.byte	 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3		.byte	 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5		.byte	 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7		.byte	 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7#ifdef IOMD_IRQREQCirq_prio_lc:	.byte	24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27		.byte	28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27		.byte	29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29		.byte	29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29		.byte	30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27		.byte	30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27		.byte	29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29		.byte	29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31		.byte	31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31#endif#ifdef IOMD_IRQREQDirq_prio_ld:	.byte	40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43		.byte	44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43		.byte	45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45		.byte	45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45		.byte	46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43		.byte	46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43		.byte	45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45		.byte	45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47		.byte	47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47#endif		.endm#elif defined(CONFIG_ARCH_EBSA110)#define IRQ_STAT		0xff000000	/* read */		.macro	disable_fiq		.endm		.macro	get_irqnr_and_base, irqnr, stat, base, tmp		mov	\base, #IRQ_STAT		ldrb	\stat, [\base]			@ get interrupts		mov	\irqnr, #0		tst	\stat, #15		addeq	\irqnr, \irqnr, #4		moveq	\stat, \stat, lsr #4		tst	\stat, #3		addeq	\irqnr, \irqnr, #2		moveq	\stat, \stat, lsr #2		tst	\stat, #1		addeq	\irqnr, \irqnr, #1		moveq	\stat, \stat, lsr #1		tst	\stat, #1			@ bit 0 should be set		.endm		.macro	irq_prio_table		.endm#elif defined(CONFIG_ARCH_SHARK)		.macro	disable_fiq		.endm		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		mov	r4, #0xe0000000		orr	r4, r4, #0x20		mov	\irqstat, #0x0C		strb	\irqstat, [r4]			@outb(0x0C, 0x20) /* Poll command */		ldrb	\irqnr, [r4]			@irq = inb(0x20) & 7		and	\irqstat, \irqnr, #0x80		teq	\irqstat, #0		beq	43f		and	\irqnr, \irqnr, #7		teq	\irqnr, #2		bne	44f43:		mov	\irqstat, #0x0C		strb	\irqstat, [r4, #0x80]		@outb(0x0C, 0xA0) /* Poll command */		ldrb	\irqnr, [r4, #0x80]		@irq = (inb(0xA0) & 7) + 8		and	\irqstat, \irqnr, #0x80		teq	\irqstat, #0		beq	44f		and	\irqnr, \irqnr, #7		add	\irqnr, \irqnr, #844:		teq	\irqstat, #0		.endm		.macro	irq_prio_table		.endm#elif defined(CONFIG_FOOTBRIDGE)#include <asm/hardware/dec21285.h>		.macro	disable_fiq		.endm		.equ	dc21285_high, ARMCSR_BASE & 0xff000000		.equ	dc21285_low, ARMCSR_BASE & 0x00ffffff		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		mov	r4, #dc21285_high		.if	dc21285_low		orr	r4, r4, #dc21285_low		.endif		ldr	\irqstat, [r4, #0x180]		@ get interrupts		mov	\irqnr, #IRQ_SDRAMPARITY		tst	\irqstat, #IRQ_MASK_SDRAMPARITY		bne	1001f		tst	\irqstat, #IRQ_MASK_UART_RX		movne	\irqnr, #IRQ_CONRX		bne	1001f		tst	\irqstat, #IRQ_MASK_DMA1		movne	\irqnr, #IRQ_DMA1		bne	1001f		tst	\irqstat, #IRQ_MASK_DMA2		movne	\irqnr, #IRQ_DMA2		bne	1001f		tst	\irqstat, #IRQ_MASK_IN0		movne	\irqnr, #IRQ_IN0		bne	1001f		tst	\irqstat, #IRQ_MASK_IN1		movne	\irqnr, #IRQ_IN1		bne	1001f		tst	\irqstat, #IRQ_MASK_IN2		movne	\irqnr, #IRQ_IN2		bne	1001f		tst	\irqstat, #IRQ_MASK_IN3		movne	\irqnr, #IRQ_IN3		bne	1001f		tst	\irqstat, #IRQ_MASK_PCI		movne	\irqnr, #IRQ_PCI		bne	1001f		tst	\irqstat, #IRQ_MASK_DOORBELLHOST		movne	\irqnr, #IRQ_DOORBELLHOST		bne     1001f			tst	\irqstat, #IRQ_MASK_I2OINPOST		movne	\irqnr, #IRQ_I2OINPOST		bne	1001f		tst	\irqstat, #IRQ_MASK_TIMER1		movne	\irqnr, #IRQ_TIMER1		bne	1001f		tst	\irqstat, #IRQ_MASK_TIMER2		movne	\irqnr, #IRQ_TIMER2		bne	1001f		tst	\irqstat, #IRQ_MASK_TIMER3		movne	\irqnr, #IRQ_TIMER3		bne	1001f		tst	\irqstat, #IRQ_MASK_UART_TX		movne	\irqnr, #IRQ_CONTX		bne	1001f		tst	\irqstat, #IRQ_MASK_PCI_ABORT		movne	\irqnr, #IRQ_PCI_ABORT		bne	1001f		tst	\irqstat, #IRQ_MASK_PCI_SERR		movne	\irqnr, #IRQ_PCI_SERR		bne	1001f		tst	\irqstat, #IRQ_MASK_DISCARD_TIMER		movne	\irqnr, #IRQ_DISCARD_TIMER		bne	1001f		tst	\irqstat, #IRQ_MASK_PCI_DPERR		movne	\irqnr, #IRQ_PCI_DPERR		bne	1001f		tst	\irqstat, #IRQ_MASK_PCI_PERR		movne	\irqnr, #IRQ_PCI_PERR1001:		.endm		.macro	irq_prio_table		.endm#elif defined(CONFIG_ARCH_NEXUSPCI)		.macro	disable_fiq		.endm		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		ldr	\irqstat, =INTCONT_BASE		ldr	\base, =soft_irq_mask		ldr	\irqstat, [\irqstat]		@ get interrupts		ldr	\base, [\base]		mov	\irqnr, #0		and	\irqstat, \irqstat, \base	@ mask out disabled ones1001:		tst	\irqstat, #1		addeq	\irqnr, \irqnr, #1		moveq	\irqstat, \irqstat, lsr #1		tsteq	\irqnr, #32		beq	1001b		teq	\irqnr, #32		.endm		.macro	irq_prio_table		.ltorg		.bssENTRY(soft_irq_mask)		.word	0		.text		.endm#elif defined(CONFIG_ARCH_TBOX)		.macro	disable_fiq		.endm		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		ldr	\irqstat, =0xffff7000		ldr	\irqstat, [\irqstat]		@ get interrupts		ldr	\base, =soft_irq_mask		ldr	\base, [\base]		mov	\irqnr, #0		and	\irqstat, \irqstat, \base	@ mask out disabled ones1001:		tst	\irqstat, #1		addeq	\irqnr, \irqnr, #1		moveq	\irqstat, \irqstat, lsr #1		tsteq	\irqnr, #32		beq	1001b		teq	\irqnr, #32		.endm		.macro	irq_prio_table		.ltorg		.bssENTRY(soft_irq_mask)		.word	0		.text		.endm#elif defined(CONFIG_ARCH_SA1100)		.macro	disable_fiq		.endm		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp		mov	r4, #0xfa000000			@ ICIP = 0xfa050000		add	r4, r4, #0x00050000		ldr	\irqstat, [r4]			@ get irqs		ldr	\irqnr, [r4, #4]		@ ICMR = 0xfa050004		ands	\irqstat, \irqstat, \irqnr		mov	\irqnr, #0		beq	1001f		tst	\irqstat, #0xff		moveq	\irqstat, \irqstat, lsr #8		addeq	\irqnr, \irqnr, #8		tsteq	\irqstat, #0xff		moveq	\irqstat, \irqstat, lsr #8		addeq	\irqnr, \irqnr, #8		tsteq	\irqstat, #0xff		moveq	\irqstat, \irqstat, lsr #8		addeq	\irqnr, \irqnr, #8		tst	\irqstat, #0x0f		moveq	\irqstat, \irqstat, lsr #4		addeq	\irqnr, \irqnr, #4		tst	\irqstat, #0x03		moveq	\irqstat, \irqstat, lsr #2		addeq	\irqnr, \irqnr, #2		tst	\irqstat, #0x01		addeqs	\irqnr, \irqnr, #11001:		.endm		.macro	irq_prio_table		.endm#elif defined(CONFIG_ARCH_L7200)#include <asm/hardware.h>			.equ	irq_base_addr,	IO_BASE_2		.macro  disable_fiq		.endm 		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp		mov     \irqstat, #irq_base_addr		@ Virt addr IRQ regs