wrpr		%o1, PSTATE_MG, %pstate	ldx		[%o0 + 0x80], %g0	ldx		[%o0 + 0x88], %g1	ldx		[%o0 + 0x90], %g2	ldx		[%o0 + 0x98], %g3	ldx		[%o0 + 0xa0], %g4	ldx		[%o0 + 0xa8], %g5	ldx		[%o0 + 0xb0], %g6	ldx		[%o0 + 0xb8], %g7	wrpr		%o5, 0x0, %pstate	retl	 nop	.globl		getcc, setccgetcc:	ldx		[%o0 + PT_V9_TSTATE], %o1	srlx		%o1, 32, %o1	and		%o1, 0xf, %o1	retl	 stx		%o1, [%o0 + PT_V9_G1]setcc:	ldx		[%o0 + PT_V9_TSTATE], %o1	ldx		[%o0 + PT_V9_G1], %o2	or		%g0, %ulo(TSTATE_ICC), %o3	sllx		%o3, 32, %o3	andn		%o1, %o3, %o1	sllx		%o2, 32, %o2	and		%o2, %o3, %o2	or		%o1, %o2, %o1	retl	 stx		%o1, [%o0 + PT_V9_TSTATE]	.globl		utrap, utrap_illutrap:	brz,pn		%g1, etrap	 nop	save		%sp, -128, %sp	rdpr		%tstate, %l6	rdpr		%cwp, %l7	andn		%l6, TSTATE_CWP, %l6	wrpr		%l6, %l7, %tstate	rdpr		%tpc, %l6	rdpr		%tnpc, %l7	wrpr		%g1, 0, %tnpc	doneutrap_ill:        call		bad_trap	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0	ba,pt		%xcc, rtrap	 clr		%l6#ifdef CONFIG_BLK_DEV_FD	.globl		floppy_hardintfloppy_hardint:	wr		%g0, (1 << 11), %clear_softint	sethi		%hi(doing_pdma), %g1	ld		[%g1 + %lo(doing_pdma)], %g2	brz,pn		%g2, floppy_dosoftint	 sethi		%hi(fdc_status), %g3	ldx		[%g3 + %lo(fdc_status)], %g3	sethi		%hi(pdma_vaddr), %g5	ldx		[%g5 + %lo(pdma_vaddr)], %g4	sethi		%hi(pdma_size), %g5	ldx		[%g5 + %lo(pdma_size)], %g5next_byte:	lduba		[%g3] ASI_PHYS_BYPASS_EC_E, %g7	andcc		%g7, 0x80, %g0	be,pn		%icc, floppy_fifo_emptied	 andcc		%g7, 0x20, %g0	be,pn		%icc, floppy_overrun	 andcc		%g7, 0x40, %g0	be,pn		%icc, floppy_write	 sub		%g5, 1, %g5	inc		%g3	lduba		[%g3] ASI_PHYS_BYPASS_EC_E, %g7	dec		%g3	orcc		%g0, %g5, %g0	stb		%g7, [%g4]	bne,pn		%xcc, next_byte	 add		%g4, 1, %g4	b,pt		%xcc, floppy_tdone	 nopfloppy_write:	ldub		[%g4], %g7	orcc		%g0, %g5, %g0	inc		%g3	stba		%g7, [%g3] ASI_PHYS_BYPASS_EC_E	dec		%g3	bne,pn		%xcc, next_byte	 add		%g4, 1, %g4floppy_tdone:	sethi		%hi(pdma_vaddr), %g1	stx		%g4, [%g1 + %lo(pdma_vaddr)]	sethi		%hi(pdma_size), %g1	stx		%g5, [%g1 + %lo(pdma_size)]	sethi		%hi(auxio_register), %g1	ldx		[%g1 + %lo(auxio_register)], %g7	lduba		[%g7] ASI_PHYS_BYPASS_EC_E, %g5	or		%g5, 0xc2, %g5	stba		%g5, [%g7] ASI_PHYS_BYPASS_EC_E	andn		%g5, 0x02, %g5	nop; nop;  nop; nop;  nop; nop;	nop; nop;  nop; nop;  nop; nop;	stba		%g5, [%g7] ASI_PHYS_BYPASS_EC_E	sethi		%hi(doing_pdma), %g1	b,pt		%xcc, floppy_dosoftint	 st		%g0, [%g1 + %lo(doing_pdma)]floppy_fifo_emptied:	sethi		%hi(pdma_vaddr), %g1	stx		%g4, [%g1 + %lo(pdma_vaddr)]	sethi		%hi(pdma_size), %g1	stx		%g5, [%g1 + %lo(pdma_size)]	sethi		%hi(irq_action), %g1	or		%g1, %lo(irq_action), %g1	ldx		[%g1 + (11 << 3)], %g3		! irqaction[floppy_irq]	ldx		[%g3 + 0x08], %g4		! action->flags>>48==ino	sethi		%hi(ivector_table), %g3	srlx		%g4, 48, %g4	or		%g3, %lo(ivector_table), %g3	sllx		%g4, 5, %g4	ldx		[%g3 + %g4], %g4		! &ivector_table[ino]	ldx		[%g4 + 0x10], %g4		! bucket->iclr	stwa		%g0, [%g4] ASI_PHYS_BYPASS_EC_E	! ICLR_IDLE	membar		#Sync				! probably not needed...	retryfloppy_overrun:	sethi		%hi(pdma_vaddr), %g1	stx		%g4, [%g1 + %lo(pdma_vaddr)]	sethi		%hi(pdma_size), %g1	stx		%g5, [%g1 + %lo(pdma_size)]	sethi		%hi(doing_pdma), %g1	st		%g0, [%g1 + %lo(doing_pdma)]floppy_dosoftint:	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	sethi		%hi(109f), %g7	b,pt		%xcc, etrap_irq109:	 or		%g7, %lo(109b), %g7	mov		11, %o0	mov		0, %o1	call		sparc_floppy_irq	 add		%sp, STACK_BIAS + REGWIN_SZ, %o2	b,pt		%xcc, rtrap	 clr		%l6#endif /* CONFIG_BLK_DEV_FD */	/* XXX Here is stuff we still need to write... -DaveM XXX */	.globl		netbsd_syscallnetbsd_syscall:	retl	 nop	/* These next few routines must be sure to clear the	 * SFSR FaultValid bit so that the fast tlb data protection	 * handler does not flush the wrong context and lock up the	 * box.	 */	.globl		__do_data_access_exception	.globl		__do_data_access_exception_tl1__do_data_access_exception_tl1:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit	membar		#Sync	ba,pt		%xcc, winfix_dax	 rdpr		%tpc, %g3__do_data_access_exception:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etrap109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		data_access_exception	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0	ba,pt		%xcc, rtrap	 clr		%l6	.globl		__do_instruction_access_exception	.globl		__do_instruction_access_exception_tl1__do_instruction_access_exception_tl1:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etraptl1	 or		%g7, %lo(109f), %g7	! Merge in below__do_instruction_access_exception:	rdpr		%pstate, %g4	wrpr		%g4, PSTATE_MG|PSTATE_AG, %pstate	mov		TLB_SFSR, %g3	mov		DMMU_SFAR, %g5	ldxa		[%g3] ASI_DMMU, %g4	! Get SFSR	ldxa		[%g5] ASI_DMMU, %g5	! Get SFAR	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit	membar		#Sync	sethi		%hi(109f), %g7	ba,pt		%xcc, etrap109:	 or		%g7, %lo(109b), %g7	mov		%l4, %o1	mov		%l5, %o2	call		instruction_access_exception	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0	ba,pt		%xcc, rtrap	 clr		%l6	/* This is the trap handler entry point for ECC correctable	 * errors.  They are corrected, but we listen for the trap	 * so that the event can be logged.	 *	 * Disrupting errors are either:	 * 1) single-bit ECC errors during UDB reads to system	 *    memory	 * 2) data parity errors during write-back events	 *	 * As far as I can make out from the manual, the CEE trap	 * is only for correctable errors during memory read	 * accesses by the front-end of the processor.	 *	 * The code below is only for trap level 1 CEE events,	 * as it is the only situation where we can safely record	 * and log.  For trap level >1 we just clear the CE bit	 * in the AFSR and return.	 */	/* Our trap handling infrastructure allows us to preserve	 * two 64-bit values during etrap for arguments to	 * subsequent C code.  Therefore we encode the information	 * as follows:	 *	 * value 1) Full 64-bits of AFAR	 * value 2) Low 33-bits of AFSR, then bits 33-->42	 *          are UDBL error status and bits 43-->52	 *          are UDBH error status	 */	.align	64	.globl	cee_trapcee_trap:	ldxa	[%g0] ASI_AFSR, %g1		! Read AFSR	ldxa	[%g0] ASI_AFAR, %g2		! Read AFAR	sllx	%g1, 31, %g1			! Clear reserved bits	srlx	%g1, 31, %g1			! in AFSR	/* NOTE: UltraSparc-I/II have high and low UDB error	 *       registers, corresponding to the two UDB units	 *       present on those chips.  UltraSparc-IIi only	 *       has a single UDB, called "SDB" in the manual.	 *       For IIi the upper UDB register always reads	 *       as zero so for our purposes things will just	 *       work with the checks below.	 */	ldxa	[%g0] ASI_UDBL_ERROR_R, %g3	! Read UDB-Low error status	andcc	%g3, (1 << 8), %g4		! Check CE bit	sllx	%g3, (64 - 10), %g3		! Clear reserved bits	srlx	%g3, (64 - 10), %g3		! in UDB-Low error status	sllx	%g3, (33 + 0), %g3		! Shift up to encoding area	or	%g1, %g3, %g1			! Or it in	be,pn	%xcc, 1f			! Branch if CE bit was clear	 nop	stxa	%g4, [%g0] ASI_UDB_ERROR_W	! Clear CE sticky bit in UDBL	membar	#Sync				! Synchronize ASI stores1:	mov	0x18, %g5			! Addr of UDB-High error status	ldxa	[%g5] ASI_UDBH_ERROR_R, %g3	! Read it	andcc	%g3, (1 << 8), %g4		! Check CE bit	sllx	%g3, (64 - 10), %g3		! Clear reserved bits	srlx	%g3, (64 - 10), %g3		! in UDB-High error status	sllx	%g3, (33 + 10), %g3		! Shift up to encoding area	or	%g1, %g3, %g1			! Or it in	be,pn	%xcc, 1f			! Branch if CE bit was clear	 nop	nop	stxa	%g4, [%g5] ASI_UDB_ERROR_W	! Clear CE sticky bit in UDBH	membar	#Sync				! Synchronize ASI stores1:	mov	1, %g5				! AFSR CE bit is	sllx	%g5, 20, %g5			! bit 20	stxa	%g5, [%g0] ASI_AFSR		! Clear CE sticky bit in AFSR	membar	#Sync				! Synchronize ASI stores	sllx	%g2, (64 - 41), %g2		! Clear reserved bits	srlx	%g2, (64 - 41), %g2		! in latched AFAR	andn	%g2, 0x0f, %g2			! Finish resv bit clearing	mov	%g1, %g4			! Move AFSR+UDB* into save reg	mov	%g2, %g5			! Move AFAR into save reg	rdpr	%pil, %g2	wrpr	%g0, 15, %pil	ba,pt	%xcc, etrap_irq	 rd	%pc, %g7	mov	%l4, %o0	mov	%l5, %o1	call	cee_log	 add	%sp, STACK_BIAS + REGWIN_SZ, %o2	ba,a,pt	%xcc, rtrap_clr_l6	/* Capture I/D/E-cache state into per-cpu error scoreboard.	 *	 * %g1:		(TL>=0) ? 1 : 0	 * %g2:		scratch	 * %g3:		scratch	 * %g4:		AFSR	 * %g5:		AFAR	 * %g6:		current thread ptr	 * %g7:		scratch	 */#define CHEETAH_LOG_ERROR						\	/* Put "TL1" software bit into AFSR. */				\	and		%g1, 0x1, %g1;					\	sllx		%g1, 63, %g2;					\	or		%g4, %g2, %g4;					\	/* Get log entry pointer for this cpu at this trap level. */	\	ldxa		[%g0] ASI_SAFARI_CONFIG, %g2;			\	srlx		%g2, 17, %g2;					\	and		%g2, 0x3ff, %g2;				\	sllx		%g2, 9, %g2;					\	sethi		%hi(cheetah_error_log), %g3;			\	ldx		[%g3 + %lo(cheetah_error_log)], %g3;		\	brz,pn		%g3, 80f;					\	 nop;								\	add		%g3, %g2, %g3;					\	sllx		%g1, 8, %g1;					\	add		%g3, %g1, %g1;					\	/* %g1 holds pointer to the top of the logging scoreboard */	\	ldx		[%g1 + 0x0], %g7;				\	cmp		%g7, -1;					\	bne,pn		%xcc, 80f;					\	 nop;								\	stx		%g4, [%g1 + 0x0];				\	stx		%g5, [%g1 + 0x8];				\	add		%g1, 0x10, %g1;					\	/* %g1 now points to D-cache logging area */			\	set		0x3ff8, %g2;	/* DC_addr mask		*/	\	and		%g5, %g2, %g2;	/* DC_addr bits of AFAR	*/	\	srlx		%g5, 12, %g3;					\	or		%g3, 1, %g3;	/* PHYS tag + valid	*/	\10:	ldxa		[%g2] ASI_DCACHE_TAG, %g7;			\	cmp		%g3, %g7;	/* TAG match?		*/	\	bne,pt		%xcc, 13f;					\	 nop;								\	/* Yep, what we want, capture state. */				\	stx		%g2, [%g1 + 0x20];				\	stx		%g7, [%g1 + 0x28];				\	/* A membar Sync is required before and after utag access. */	\	membar		#Sync;						\	ldxa		[%g2] ASI_DCACHE_UTAG, %g7;			\	membar		#Sync;						\	stx		%g7, [%g1 + 0x30];				\	ldxa		[%g2] ASI_DCACHE_SNOOP_TAG, %g7;		\	stx		%g7, [%g1 + 0x38];				\	clr		%g3;						\12:	ldxa		[%g2 + %g3] ASI_DCACHE_DATA, %g7;		\	stx		%g7, [%g1];					\	add		%g3, (1 << 5), %g3;				\	cmp		%g3, (4 << 5);					\	bl,pt		%xcc, 12b;					\	 add		%g1, 0x8, %g1;					\	ba,pt		%xcc, 20f;					\	 add		%g1, 0x20, %g1;					\13:	sethi		%hi(1 << 14), %g7;				\	add		%g2, %g7, %g2;					\	srlx		%g2, 14, %g7;					\	cmp		%g7, 4;						\	bl,pt		%xcc, 10b;					\	 nop;								\	add		%g1, 0x40, %g1;					\20:	/* %g1 now points to I-cache logging area */			\	set		0x1fe0, %g2;	/* IC_addr mask		*/	\	and		%g5, %g2, %g2;	/* IC_addr bits of AFAR	*/	\	sllx		%g2, 1, %g2;	/* IC_addr[13:6]==VA[12:5] */	\	srlx		%g5, (13 - 8), %g3; /* Make PTAG */		\	andn		%g3, 0xff, %g3;	/* Mask off undefined bits */	\21:	ldxa		[%g2] ASI_IC_TAG, %g7;				\	andn		%g7, 0xff, %g7;					\	cmp		%g3, %g7;					\	bne,pt		%xcc, 23f;					\	 nop;								\	/* Yep, what we want, capture state. */				\	stx		%g2, [%g1 + 0x40];				\	stx		%g7, [%g1 + 0x48];				\	add		%g2, (1 << 3), %g2;				\	ldxa		[%g2] ASI_IC_TAG, %g7;				\	add		%g2, (1 << 3), %g2;				\	stx		%g7, [%g1 + 0x50];				\	ldxa		[%g2] ASI_IC_TAG, %g7;				\	add		%g2, (1 << 3), %g2;				\	stx		%g7, [%g1 + 0x60];				\	ldxa		[%g2] ASI_IC_TAG, %g7;				\	stx		%g7, [%g1 + 0x68];				\	sub		%g2, (3 << 3), %g2;				\	ldxa		[%g2] ASI_IC_STAG, %g7;				\	stx		%g7, [%g1 + 0x58];				\	clr		%g3;						\	srlx		%g2, 2, %g2;					\22:	ldxa		[%g2 + %g3] ASI_IC_INSTR, %g7;			\	stx		%g7, [%g1];					\	add		%g3, (1 << 3), %g3;				\	cmp		%g3, (8 << 3);					\	bl,pt		%xcc, 22b;					\	 add		%g1, 0x8, %g1;					\	ba,pt		%xcc, 30f;					\	 add		%g1, 0x30, %g1;					\23:	sethi		%hi(1 << 14), %g7;				\	add		%g2, %g7, %g2;					\	srlx		%g2, 14, %g7;					\	cmp		%g7, 4;						\	bl,pt		%xcc, 21b;					\	 nop;								\	add		%g1, 0x70, %g1;					\30:	/* %g1 now points to E-cache logging area */			\	andn		%g5, (32 - 1), %g2;	/* E-cache subblock */	\	stx		%g2, [%g1 + 0x20];				\	ldxa		[%g2] ASI_EC_TAG_DATA, %g7;			\	stx		%g7, [%g1 + 0x28];				\	ldxa		[%g2] ASI_EC_R, %g0;				\	clr		%g3;						\31:	ldxa		[%g3] ASI_EC_DATA, %g7;				\	stx		%g7, [%g1 + %g3];				\	add		%g3, 0x8, %g3;					\	cmp		%g3, 0x20;					\	bl,pt		%xcc, 31b;					\	 nop;								\80:	/* DONE */	/* These get patched into the trap table at boot time	 * once we know we have a cheetah processor.	 */	.globl		cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1cheetah_fecc_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_DC | DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_fast_ecc), %g2	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0	 mov		0, %g1cheetah_fecc_trap_vector_tl1:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_DC | DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_fast_ecc), %g2	jmpl		%g2 + %lo(cheetah_fast_ecc), %g0	 mov		1, %g1	.globl	cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1cheetah_cee_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_cee), %g2	jmpl		%g2 + %lo(cheetah_cee), %g0	 mov		0, %g1cheetah_cee_trap_vector_tl1:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1	andn		%g1, DCU_IC, %g1	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG	membar		#Sync	sethi		%hi(cheetah_cee), %g2	jmpl		%g2 + %lo(cheetah_cee), %g0	 mov		1, %g1	.globl	cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1cheetah_deferred_trap_vector:	membar		#Sync	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;	andn		%g1, DCU_DC | DCU_IC, %g1;	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;	membar		#Sync;	sethi		%hi(cheetah_deferred_trap), %g2	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0	 mov		0, %g1cheetah_deferred_trap_vector_tl1:	membar		#Sync;	ldxa		[%g0] ASI_DCU_CONTROL_REG, %g1;	andn		%g1, DCU_DC | DCU_IC, %g1;	stxa		%g1, [%g0] ASI_DCU_CONTROL_REG;	membar		#Sync;	sethi		%hi(cheetah_deferred_trap), %g2	jmpl		%g2 + %lo(cheetah_deferred_trap), %g0	 mov		1, %g1	/* Cheetah FECC trap handling, we get here from tl{0,1}_fecc	 * in the trap table.  That code has done a memory barrier	 * and has disabled both the I-cache and D-cache in the DCU	 * control register.  The I-cache is disabled so that we may	 * capture the corrupted cache line, and the D-cache is disabled	 * because corrupt data may have been placed there and we don't	 * want to reference it.	 *	 * %g1 is one if this trap occured at %tl >= 1.	 *	 * Next, we turn off error reporting so that we don't recurse.	 */	.globl		cheetah_fast_ecccheetah_fast_ecc:	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g2	andn		%g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2	stxa		%g2, [%g0] ASI_ESTATE_ERROR_EN	membar		#Sync	/* Fetch and clear AFSR/AFAR */	ldxa		[%g0] ASI_AFSR, %g4	ldxa		[%g0] ASI_AFAR, %g5	stxa		%g4, [%g0] ASI_AFSR	membar		#Sync	CHEETAH_LOG_ERROR	rdpr		%pil, %g2	wrpr		%g0, 15, %pil	ba,pt		%xcc, etrap_irq	 rd		%pc, %g7	mov		%l4, %o1	mov		%l5, %o2	call		cheetah_fecc_handler	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0	ba,a,pt		%xcc, rtrap_clr_l6	/* Our caller has disabled I-cache and performed membar Sync. */	.globl		cheetah_ceecheetah_cee:	ldxa		[%g0] ASI_ESTATE_ERROR_EN, %g2	andn		%g2, ESTATE_ERROR_CEEN, %g2	stxa		%g2, [%g0] ASI_ESTATE_ERROR_EN	membar		#Sync	/* Fetch and clear AFSR/AFAR */	ldxa		[%g0] ASI_AFSR, %g4	ldxa		[%g0] ASI_AFAR, %g5