/* *	linux/arch/alpha/kernel/core_mcpcia.c * * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com). * * Code common to all MCbus-PCI Adaptor core logic chipsets */#include <linux/kernel.h>#include <linux/types.h>#include <linux/pci.h>#include <linux/sched.h>#include <linux/init.h>#include <linux/delay.h>#include <asm/ptrace.h>#include <asm/system.h>#include <asm/hwrpb.h>#define __EXTERN_INLINE inline#include <asm/io.h>#include <asm/core_mcpcia.h>#undef __EXTERN_INLINE#include "proto.h"#include "pci_impl.h"/* * NOTE: Herein lie back-to-back mb instructions.  They are magic.  * One plausible explanation is that the i/o controller does not properly * handle the system transaction.  Another involves timing.  Ho hum. *//* * BIOS32-style PCI interface: */#define DEBUG_CFG 0#if DEBUG_CFG# define DBG_CFG(args)	printk args#else# define DBG_CFG(args)#endif#define MCPCIA_MAX_HOSES 4/* * Given a bus, device, and function number, compute resulting * configuration space address and setup the MCPCIA_HAXR2 register * accordingly.  It is therefore not safe to have concurrent * invocations to configuration space access routines, but there * really shouldn't be any need for this. * * Type 0: * *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * *	31:11	Device select bit. * 	10:8	Function number * 	 7:2	Register number * * Type 1: * *  3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1  *  3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * *	31:24	reserved *	23:16	bus number (8 bits = 128 possible buses) *	15:11	Device number (5 bits) *	10:8	function number *	 7:2	register number *   * Notes: *	The function number selects which function of a multi-function device  *	(e.g., SCSI and Ethernet). *  *	The register selects a DWORD (32 bit) register offset.  Hence it *	doesn't get shifted by 2 bits as we want to "drop" the bottom two *	bits. */static unsigned intconf_read(unsigned long addr, unsigned char type1,	  struct pci_controller *hose){	unsigned long flags;	unsigned long mid = MCPCIA_HOSE2MID(hose->index);	unsigned int stat0, value, temp, cpu;	cpu = smp_processor_id();	__save_and_cli(flags);	DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n",		 addr, type1, mid));	/* Reset status register to avoid losing errors.  */	stat0 = *(vuip)MCPCIA_CAP_ERR(mid);	*(vuip)MCPCIA_CAP_ERR(mid) = stat0;	mb();	temp = *(vuip)MCPCIA_CAP_ERR(mid);	DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));	mb();	draina();	mcheck_expected(cpu) = 1;	mcheck_taken(cpu) = 0;	mcheck_extra(cpu) = mid;	mb();	/* Access configuration space.  */	value = *((vuip)addr);	mb();	mb();  /* magic */	if (mcheck_taken(cpu)) {		mcheck_taken(cpu) = 0;		value = 0xffffffffU;		mb();	}	mcheck_expected(cpu) = 0;	mb();	DBG_CFG(("conf_read(): finished\n"));	__restore_flags(flags);	return value;}static voidconf_write(unsigned long addr, unsigned int value, unsigned char type1,	   struct pci_controller *hose){	unsigned long flags;	unsigned long mid = MCPCIA_HOSE2MID(hose->index);	unsigned int stat0, temp, cpu;	cpu = smp_processor_id();	__save_and_cli(flags);	/* avoid getting hit by machine check */	/* Reset status register to avoid losing errors.  */	stat0 = *(vuip)MCPCIA_CAP_ERR(mid);	*(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();	temp = *(vuip)MCPCIA_CAP_ERR(mid);	DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));	draina();	mcheck_expected(cpu) = 1;	mcheck_extra(cpu) = mid;	mb();	/* Access configuration space.  */	*((vuip)addr) = value;	mb();	mb();  /* magic */	temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */	mcheck_expected(cpu) = 0;	mb();	DBG_CFG(("conf_write(): finished\n"));	__restore_flags(flags);}static intmk_conf_addr(struct pci_dev *dev, int where, struct pci_controller *hose,	     unsigned long *pci_addr, unsigned char *type1){	u8 bus = dev->bus->number;	u8 devfn = dev->devfn;	unsigned long addr;	DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x,"		 " pci_addr=0x%p, type1=0x%p)\n",		 bus, devfn, hose->index, where, pci_addr, type1));	/* Type 1 configuration cycle for *ALL* busses.  */	*type1 = 1;	if (dev->bus->number == hose->first_busno)		bus = 0;	addr = (bus << 16) | (devfn << 8) | (where);	addr <<= 5; /* swizzle for SPARSE */	addr |= hose->config_space_base;	*pci_addr = addr;	DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));	return 0;}static intmcpcia_read_config_byte(struct pci_dev *dev, int where, u8 *value){	struct pci_controller *hose = dev->sysdata;	unsigned long addr, w;	unsigned char type1;	if (mk_conf_addr(dev, where, hose, &addr, &type1))		return PCIBIOS_DEVICE_NOT_FOUND;	addr |= 0x00;	w = conf_read(addr, type1, hose);	*value = __kernel_extbl(w, where & 3);	return PCIBIOS_SUCCESSFUL;}static intmcpcia_read_config_word(struct pci_dev *dev, int where, u16 *value){	struct pci_controller *hose = dev->sysdata;	unsigned long addr, w;	unsigned char type1;	if (mk_conf_addr(dev, where, hose, &addr, &type1))		return PCIBIOS_DEVICE_NOT_FOUND;	addr |= 0x08;	w = conf_read(addr, type1, hose);	*value = __kernel_extwl(w, where & 3);	return PCIBIOS_SUCCESSFUL;}static intmcpcia_read_config_dword(struct pci_dev *dev, int where, u32 *value){	struct pci_controller *hose = dev->sysdata;	unsigned long addr;	unsigned char type1;	if (mk_conf_addr(dev, where, hose, &addr, &type1))		return PCIBIOS_DEVICE_NOT_FOUND;	addr |= 0x18;	*value = conf_read(addr, type1, hose);	return PCIBIOS_SUCCESSFUL;}static intmcpcia_write_config(struct pci_dev *dev, int where, u32 value, long mask){	struct pci_controller *hose = dev->sysdata;	unsigned long addr;	unsigned char type1;	if (mk_conf_addr(dev, where, hose, &addr, &type1))		return PCIBIOS_DEVICE_NOT_FOUND;	addr |= mask;	value = __kernel_insql(value, where & 3);	conf_write(addr, value, type1, hose);	return PCIBIOS_SUCCESSFUL;}static intmcpcia_write_config_byte(struct pci_dev *dev, int where, u8 value){	return mcpcia_write_config(dev, where, value, 0x00);}static intmcpcia_write_config_word(struct pci_dev *dev, int where, u16 value){	return mcpcia_write_config(dev, where, value, 0x08);}static intmcpcia_write_config_dword(struct pci_dev *dev, int where, u32 value){	return mcpcia_write_config(dev, where, value, 0x18);}struct pci_ops mcpcia_pci_ops = {	read_byte:	mcpcia_read_config_byte,	read_word:	mcpcia_read_config_word,	read_dword:	mcpcia_read_config_dword,	write_byte:	mcpcia_write_config_byte,	write_word:	mcpcia_write_config_word,	write_dword:	mcpcia_write_config_dword};voidmcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end){	wmb();	*(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0;	mb();}static int __initmcpcia_probe_hose(int h){	int cpu = smp_processor_id();	int mid = MCPCIA_HOSE2MID(h);	unsigned int pci_rev;	/* Gotta be REAL careful.  If hose is absent, we get an mcheck.  */	mb();	mb();	draina();	wrmces(7);	mcheck_expected(cpu) = 2;	/* indicates probing */	mcheck_taken(cpu) = 0;	mcheck_extra(cpu) = mid;	mb();	/* Access the bus revision word. */	pci_rev = *(vuip)MCPCIA_REV(mid);	mb();	mb();  /* magic */	if (mcheck_taken(cpu)) {		mcheck_taken(cpu) = 0;		pci_rev = 0xffffffff;		mb();	}	mcheck_expected(cpu) = 0;	mb();	return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST;}