/* *	Low-Level PCI Support for PC -- Routing of Interrupts * *	(c) 1999--2000 Martin Mares <mj@ucw.cz> */#include <linux/config.h>#include <linux/types.h>#include <linux/kernel.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/slab.h>#include <linux/interrupt.h>#include <linux/irq.h>#include <asm/io.h>#include <asm/smp.h>#include <asm/io_apic.h>#include "pci-i386.h"#define PIRQ_SIGNATURE	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))#define PIRQ_VERSION 0x0100static struct irq_routing_table *pirq_table;/* * Never use: 0, 1, 2 (timer, keyboard, and cascade) * Avoid using: 13, 14 and 15 (FP error and IDE). * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) */unsigned int pcibios_irq_mask = 0xfff8;static int pirq_penalty[16] = {	1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,	0, 0, 0, 0, 1000, 100000, 100000, 100000};struct irq_router {	char *name;	u16 vendor, device;	int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);	int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);};/* *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. */static struct irq_routing_table * __init pirq_find_routing_table(void){	u8 *addr;	struct irq_routing_table *rt;	int i;	u8 sum;	for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {		rt = (struct irq_routing_table *) addr;		if (rt->signature != PIRQ_SIGNATURE ||		    rt->version != PIRQ_VERSION ||		    rt->size % 16 ||		    rt->size < sizeof(struct irq_routing_table))			continue;		sum = 0;		for(i=0; i<rt->size; i++)			sum += addr[i];		if (!sum) {			DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);			return rt;		}	}	return NULL;}/* *  If we have a IRQ routing table, use it to search for peer host *  bridges.  It's a gross hack, but since there are no other known *  ways how to get a list of buses, we have to go this way. */static void __init pirq_peer_trick(void){	struct irq_routing_table *rt = pirq_table;	u8 busmap[256];	int i;	struct irq_info *e;	memset(busmap, 0, sizeof(busmap));	for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {		e = &rt->slots[i];#ifdef DEBUG		{			int j;			DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);			for(j=0; j<4; j++)				DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);			DBG("\n");		}#endif		busmap[e->bus] = 1;	}	for(i=1; i<256; i++)		/*		 *  It might be a secondary bus, but in this case its parent is already		 *  known (ascending bus order) and therefore pci_scan_bus returns immediately.		 */		if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))			printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);	pcibios_last_bus = -1;}/* *  Code for querying and setting of IRQ routes on various interrupt routers. */static void eisa_set_level_irq(unsigned int irq){	unsigned char mask = 1 << (irq & 7);	unsigned int port = 0x4d0 + (irq >> 3);	unsigned char val = inb(port);	if (!(val & mask)) {		DBG(" -> edge");		outb(val | mask, port);	}}/* * Common IRQ routing practice: nybbles in config space, * offset by some magic constant. */static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr){	u8 x;	unsigned reg = offset + (nr >> 1);	pci_read_config_byte(router, reg, &x);	return (nr & 1) ? (x >> 4) : (x & 0xf);}static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val){	u8 x;	unsigned reg = offset + (nr >> 1);	pci_read_config_byte(router, reg, &x);	x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);	pci_write_config_byte(router, reg, x);}/* * ALI pirq entries are damn ugly, and completely undocumented. * This has been figured out from pirq tables, and it's not a pretty * picture. */static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };	return irqmap[read_config_nybble(router, 0x48, pirq-1)];}static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };	unsigned int val = irqmap[irq];			if (val) {		write_config_nybble(router, 0x48, pirq-1, val);		return 1;	}	return 0;}/* * The Intel PIIX4 pirq rules are fairly simple: "pirq" is * just a pointer to the config space. */static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	u8 x;	pci_read_config_byte(router, pirq, &x);	return (x < 16) ? x : 0;}static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	pci_write_config_byte(router, pirq, irq);	return 1;}/* * The VIA pirq rules are nibble-based, like ALI, * but without the ugly irq number munging. */static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	return read_config_nybble(router, 0x55, pirq);}static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	write_config_nybble(router, 0x55, pirq, irq);	return 1;}/* * OPTI: high four bits are nibble pointer.. * I wonder what the low bits do? */static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	return read_config_nybble(router, 0xb8, pirq >> 4);}static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	write_config_nybble(router, 0xb8, pirq >> 4, irq);	return 1;}/* * Cyrix: nibble offset 0x5C */static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	return read_config_nybble(router, 0x5C, (pirq-1)^1);}static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	write_config_nybble(router, 0x5C, (pirq-1)^1, irq);	return 1;}/* *	PIRQ routing for SiS 85C503 router used in several SiS chipsets *	According to the SiS 5595 datasheet (preliminary V1.0, 12/24/1997) *	the related registers work as follows: *	 *	general: one byte per re-routable IRQ, *		 bit 7      IRQ mapping enabled (0) or disabled (1) *		 bits [6:4] reserved *		 bits [3:0] IRQ to map to *		     allowed: 3-7, 9-12, 14-15 *		     reserved: 0, 1, 2, 8, 13 * *	individual registers in device config space: * *	0x41/0x42/0x43/0x44:	PCI INT A/B/C/D - bits as in general case * *	0x61:			IDEIRQ: bits as in general case - but: *				bits [6:5] must be written 01 *				bit 4 channel-select primary (0), secondary (1) * *	0x62:			USBIRQ: bits as in general case - but: *				bit 4 OHCI function disabled (0), enabled (1) *	 *	0x6a:			ACPI/SCI IRQ - bits as in general case * *	0x7e:			Data Acq. Module IRQ - bits as in general case * *	Apparently there are systems implementing PCI routing table using both *	link values 0x01-0x04 and 0x41-0x44 for PCI INTA..D, but register offsets *	like 0x62 as link values for USBIRQ e.g. So there is no simple *	"register = offset + pirq" relation. *	Currently we support PCI INTA..D and USBIRQ and try our best to handle *	both link mappings. *	IDE/ACPI/DAQ mapping is currently unsupported (left untouched as set by BIOS). */static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	u8 x;	int reg = pirq;	switch(pirq) {		case 0x01:		case 0x02:		case 0x03:		case 0x04:			reg += 0x40;		case 0x41:		case 0x42:		case 0x43:		case 0x44:		case 0x62:			pci_read_config_byte(router, reg, &x);			if (reg != 0x62)				break;			if (!(x & 0x40))				return 0;			break;		case 0x61:		case 0x6a:		case 0x7e:			printk(KERN_INFO "SiS pirq: advanced IDE/ACPI/DAQ mapping not yet implemented\n");			return 0;		default:						printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);			return 0;	}	return (x & 0x80) ? 0 : (x & 0x0f);}static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	u8 x;	int reg = pirq;	switch(pirq) {		case 0x01:		case 0x02:		case 0x03:		case 0x04:			reg += 0x40;		case 0x41:		case 0x42:		case 0x43:		case 0x44:		case 0x62:			x = (irq&0x0f) ? (irq&0x0f) : 0x80;			if (reg != 0x62)				break;			/* always mark OHCI enabled, as nothing else knows about this */			x |= 0x40;			break;		case 0x61:		case 0x6a:		case 0x7e:			printk(KERN_INFO "advanced SiS pirq mapping not yet implemented\n");			return 0;		default:						printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq);			return 0;	}	pci_write_config_byte(router, reg, x);	return 1;}/* * VLSI: nibble offset 0x74 - educated guess due to routing table and *       config space of VLSI 82C534 PCI-bridge/router (1004:0102) *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 *       for the busbridge to the docking station. */static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq){	if (pirq > 8) {		printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);		return 0;	}	return read_config_nybble(router, 0x74, pirq-1);}static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq){	if (pirq > 8) {		printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);		return 0;	}	write_config_nybble(router, 0x74, pirq-1, irq);	return 1;}/* * ServerWorks: PCI interrupts mapped to system IRQ lines through Index * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect * register is a straight binary coding of desired PIC IRQ (low nibble). * * The 'link' value in the PIRQ table is already in the correct format * for the Index register.  There are some special index values: