/*   * Simple synchronous serial port driver for ETRAX 100LX. * * Synchronous serial ports are used for continous streamed data like audio. * The default setting for this driver is compatible with the STA 013 MP3 * decoder. The driver can easily be tuned to fit other audio encoder/decoders * and SPI * * Copyright (c) 2001 Axis Communications AB *  * Author: Mikael Starvik  * */#include <linux/module.h>#include <linux/kernel.h>#include <linux/config.h>#include <linux/types.h>#include <linux/errno.h>#include <linux/major.h>#include <linux/sched.h>#include <linux/slab.h>#include <linux/interrupt.h>#include <linux/init.h>#include <linux/timer.h>#include <asm/irq.h>#include <asm/io.h>#include <asm/svinto.h>#include <asm/uaccess.h>#include <asm/system.h>#include <asm/sync_serial.h>/* The receiver is a bit tricky beacuse of the continous stream of data. *//*                                                                       *//* Two DMA descriptors are linked together. Each DMA descriptor is       *//* responsible for one half of a common buffer.                          *//*                                                                       *//* ------------------------------                                        *//* |   ----------   ----------	|                                        *//* --> | Descr1 |-->| Descr2 |---                                        *//*     ----------   ----------                                           *//*         |            |                                                *//*         v            v                                                *//*   -----------------------------                                       *//*   |        BUFFER             |                                       *//*   -----------------------------                                       *//*      |             |                                                  *//*    readp          writep                                              *//*                                                                       *//* If the application keeps up the pace readp will be right after writep.*//* If the application can't keep the pace we have to throw away data.    */ /* The idea is that readp should be ready with the data pointed out by	 *//* Descr1 when the DMA has filled in Descr2. Otherwise we will discard	 *//* the rest of the data pointed out by Descr1 and set readp to the start *//* of Descr2                                                             */#define SYNC_SERIAL_MAJOR 125/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit *//* words can be handled */#define IN_BUFFER_SIZE 12288#define OUT_BUFFER_SIZE 4096#define DEFAULT_FRAME_RATE 0#define DEFAULT_WORD_RATE 7#define DEBUG(x) /* Define some macros to access ETRAX 100 registers */#define SETF(var, reg, field, val) var = (var & ~IO_MASK(##reg##, field)) | \					  IO_FIELD(##reg##, field, val)#define SETS(var, reg, field, val) var = (var & ~IO_MASK(##reg##, field)) | \					  IO_STATE(##reg##, field, val)typedef struct sync_port{	/* Etrax registers and bits*/	volatile unsigned * const status;	volatile unsigned * const ctrl_data;	volatile unsigned * const output_dma_first;	volatile unsigned char * const output_dma_cmd;	volatile unsigned char * const output_dma_clr_irq;	volatile unsigned * const input_dma_first;	volatile unsigned char * const input_dma_cmd;	volatile unsigned char * const input_dma_clr_irq;	volatile unsigned * const data_out;	volatile unsigned * const data_in;	char data_avail_bit; /* In R_IRQ_MASK1_RD */	char transmitter_ready_bit; /* In R_IRQ_MASK1_RD */	char ready_irq_bit; /* In R_IRQ_MASK1_SET and R_IRQ_MASK1_CLR */	char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */	char output_dma_bit; /* In R_IRQ_MASK2_RD */	int enabled;  /* 1 if port is enabled */	int use_dma;  /* 1 if port uses dma */	int port_nbr; /* Port 0 or 1 */	unsigned ctrl_data_shadow; /* Register shadow */	char busy; /* 1 if port is busy */	wait_queue_head_t out_wait_q;	wait_queue_head_t in_wait_q;	struct etrax_dma_descr out_descr;	struct etrax_dma_descr in_descr1;	struct etrax_dma_descr in_descr2;	char out_buffer[OUT_BUFFER_SIZE];	int out_count; /* Remaining bytes for current transfer */	char* outp; /* Current position in out_buffer */	char in_buffer[IN_BUFFER_SIZE];	volatile char* readp;  /* Next byte to be read by application */	volatile char* writep; /* Next byte to be written by etrax */	int odd_output; /* 1 if writing odd nible in 12 bit mode */	int odd_input;  /* 1 if reading odd nible in 12 bit mode */} sync_port;static int etrax_sync_serial_init(void);static void initialize_port(int portnbr);static int sync_serial_open(struct inode *, struct file*);static int sync_serial_release(struct inode*, struct file*);static int sync_serial_ioctl(struct inode*, struct file*,			     unsigned int cmd, unsigned long arg);static ssize_t sync_serial_write(struct file * file, const char * buf, 				 size_t count, loff_t *ppos);static ssize_t sync_serial_manual_write(struct file * file, const char * buf, 					size_t count, loff_t *ppos);static ssize_t sync_serial_read(struct file *file, char *buf, 				size_t count, loff_t *ppos);static void send_word(sync_port* port);static void start_dma(struct sync_port *port, const char* data, int count);static void start_dma_in(sync_port* port);static void tr_interrupt(int irq, void *dev_id, struct pt_regs * regs);static void rx_interrupt(int irq, void *dev_id, struct pt_regs * regs);static void manual_interrupt(int irq, void *dev_id, struct pt_regs * regs);/* The ports */static struct sync_port ports[]={	{		R_SYNC_SERIAL1_STATUS,  /* status */		R_SYNC_SERIAL1_CTRL,    /* ctrl_data */		R_DMA_CH8_FIRST,        /* output_dma_first */		R_DMA_CH8_CMD,          /* output_dma_cmd */		R_DMA_CH8_CLR_INTR,     /* output_dma_clr_irq */		R_DMA_CH9_FIRST,        /* input_dma_first */		R_DMA_CH9_CMD,          /* input_dma_cmd */		R_DMA_CH9_CLR_INTR,     /* input_dma_clr_irq */		R_SYNC_SERIAL1_TR_DATA, /* data_out */		R_SYNC_SERIAL1_REC_DATA,/* data in */		IO_BITNR(R_IRQ_MASK1_RD, ser1_data),   /* data_avail_bit */		IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),  /* transmitter_ready_bit */		IO_BITNR(R_IRQ_MASK1_SET, ser1_ready), /* ready_irq_bit */		IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),  /* input_dma_descr_bit */		IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),    /* output_dma_bit */	},	{		R_SYNC_SERIAL3_STATUS,  /* status */		R_SYNC_SERIAL3_CTRL,    /* ctrl_data */		R_DMA_CH4_FIRST,        /* output_dma_first */		R_DMA_CH4_CMD,          /* output_dma_cmd */		R_DMA_CH4_CLR_INTR,     /* output_dma_clr_irq */		R_DMA_CH5_FIRST,        /* input_dma_first */		R_DMA_CH5_CMD,          /* input_dma_cmd */		R_DMA_CH5_CLR_INTR,     /* input_dma_clr_irq */		R_SYNC_SERIAL3_TR_DATA, /* data_out */		R_SYNC_SERIAL3_REC_DATA,/* data in */		IO_BITNR(R_IRQ_MASK1_RD, ser3_data),   /* data_avail_bit */		IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),  /* transmitter_ready_bit */		IO_BITNR(R_IRQ_MASK1_SET, ser3_ready), /* ready_irq_bit */		IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),  /* input_dma_descr_bit */		IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),    /* output_dma_bit */	}};/* Register shadows */static unsigned sync_serial_prescale_shadow = 0;static unsigned gen_config_ii_shadow = 0;#define NUMBER_OF_PORTS (sizeof(ports)/sizeof(sync_port))static struct file_operations sync_serial_fops = {       owner:	THIS_MODULE,       write:	sync_serial_write,       read:	sync_serial_read,       ioctl:	sync_serial_ioctl,       open:	sync_serial_open,       release: sync_serial_release};static int __init etrax_sync_serial_init(void){	ports[0].enabled = 0;	ports[1].enabled = 0;	if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 ) 	{		printk("unable to get major for synchronous serial port\n");		return -EBUSY;	}	/* Deselect synchronous serial ports */	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, ser3, select);	*R_GEN_CONFIG_II = gen_config_ii_shadow;  	/* Initialize Ports */#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)	ports[0].enabled = 1;	SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); 	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)	ports[0].use_dma = 1;	initialize_port(0);	if(request_irq(24, tr_interrupt, 0, "synchronous serial 1 dma tr", &ports[0]))		 panic("Can't allocate sync serial port 1 IRQ");	if(request_irq(25, rx_interrupt, 0, "synchronous serial 1 dma rx", &ports[0]))		panic("Can't allocate sync serial port 1 IRQ");	RESET_DMA(8); WAIT_DMA(8);	RESET_DMA(9); WAIT_DMA(9);	*R_DMA_CH8_CLR_INTR = IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |	  IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); 	*R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do) |	  IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, do); 	*R_IRQ_MASK2_SET =	  IO_STATE(R_IRQ_MASK2_SET, dma8_eop, set) |	  IO_STATE(R_IRQ_MASK2_SET, dma8_descr, set) |          IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set);	start_dma_in(&ports[0]);#else	ports[0].use_dma = 0;	initialize_port(0);	if (request_irq(8, manual_interrupt, SA_SHIRQ, "synchronous serial manual irq", &ports[0]))		panic("Can't allocate sync serial manual irq");	*R_IRQ_MASK1_SET = IO_STATE(R_IRQ_MASK1_SET, ser1_data, set);	 #endif#endif#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)	ports[1].enabled = 1;	SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);	SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)	ports[1].use_dma = 1;	initialize_port(1);	if(request_irq(20, tr_interrupt, 0, "synchronous serial 3 dma tr", &ports[1]))		panic("Can't allocate sync serial port 1 IRQ");	if(request_irq(21, rx_interrupt, 0, "synchronous serial 3 dma rx", &ports[1]))		panic("Can't allocate sync serial port 1 IRQ");	RESET_DMA(4); WAIT_DMA(4);	RESET_DMA(5); WAIT_DMA(5);	*R_DMA_CH4_CLR_INTR = IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |	  IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); 	*R_DMA_CH5_CLR_INTR = IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, do) |	  IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, do); 	*R_IRQ_MASK2_SET =	  IO_STATE(R_IRQ_MASK2_SET, dma4_eop, set) |	  IO_STATE(R_IRQ_MASK2_SET, dma4_descr, set) |	  IO_STATE(R_IRQ_MASK2_SET, dma5_descr, set);	start_dma_in(&ports[1]);#else	ports[1].use_dma = 0;		initialize_port(1);	if (port[0].use_dma) /* Port 0 uses dma, we must manual allocate IRQ */	{		if (request_irq(8, manual_interrupt, SA_SHIRQ, "synchronous serial manual irq", &ports[1]))			panic("Can't allocate sync serial manual irq");	}	*R_IRQ_MASK1_SET = IO_STATE(R_IRQ_MASK1_SET, ser3_data, set);	 #endif#endif	*R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */	/* Set up timing */	*R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (	  IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | 	  IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | 	  IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | 	  IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | 	  IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | 	  IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, DEFAULT_FRAME_RATE) | 	  IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | 	  IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));	/* Select synchronous ports */	*R_GEN_CONFIG_II = gen_config_ii_shadow;	printk("ETRAX 100LX synchronous serial port driver\n");	return 0;}static void initialize_port(int portnbr){	struct sync_port* port = &ports[portnbr];	DEBUG(printk("Init sync serial port %d\n", portnbr));    	port->port_nbr = portnbr;		port->busy = 0;			port->readp = port->in_buffer;	port->writep = port->in_buffer + IN_BUFFER_SIZE/2;