?? xhm.mdl
字號:
Model {
Name "xhm"
Version 5.0
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
ExecutionOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Sun Jun 08 23:35:04 2008"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "chenxiabing"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Mon Jun 09 09:35:42 2008"
ModelVersionFormat "1.%<AutoIncrement:4>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType CombinatorialLogic
TruthTable "[0 0;0 1;0 1;1 0;0 1;1 0;1 0;1 1]"
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
ShowAdditionalParam off
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
}
Block {
BlockType DataTypeConversion
DataType "auto"
SaturateOnIntegerOverflow on
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ShowAdditionalParam off
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
PortDimensions "-1"
SampleTime "-1"
ShowAdditionalParam off
LatchInput off
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
Interpolate on
}
Block {
BlockType Math
Operator "exp"
OutputSignalType "auto"
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Reference
}
Block {
BlockType RelationalOperator
Operator ">="
ShowAdditionalParam off
InputSameDT on
LogicOutDataTypeMode "Logical (see Advanced Sim. Parameters)"
LogicDataType "uint(8)"
ZeroCross on
}
Block {
BlockType Selector
InputType "Vector"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "xhm"
Location [516, 365, 1096, 679]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AWGN\nChannel"
Ports [1, 1]
Position [335, 79, 415, 121]
SourceBlock "commchan2/AWGN\nChannel"
SourceType "AWGN Channel"
seed "54321"
noiseMode "Signal to noise ratio (SNR)"
EsNodB "10"
SNRdB "M"
Ps "1"
Tsym "1"
variance "1"
}
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [20, 78, 100, 122]
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
P "0.5"
seed "12345"
Ts "0.001"
frameBased on
sampPerFrame "4"
orient off
}
Block {
BlockType Reference
Name "Binary\nCyclic Decoder"
Ports [1, 1]
Position [275, 183, 355, 227]
Orientation "left"
SourceBlock "commblkcod2/Binary\nCyclic Decoder"
SourceType "Binary Cyclic Decoder"
n "7"
p "4"
}
Block {
BlockType Reference
Name "Binary\nCyclic Encoder"
Ports [1, 1]
Position [130, 78, 210, 122]
SourceBlock "commblkcod2/Binary\nCyclic Encoder"
SourceType "Binary Cyclic Encoder"
n "7"
p "4"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2]
Position [20, 167, 95, 218]
Orientation "left"
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Workspace"
WsName "ErrorVec"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Block {
BlockType Reference
Name "M-FSK\nDemodulator\nBaseband"
Ports [1, 1]
Position [435, 76, 510, 124]
SourceBlock "commdigbbndfm2/M-FSK\nDemodulator\nBaseband"
SourceType "M-FSK Demodulator Baseband"
M "2"
OutType "Integer"
Dec "Binary"
freqSep "6"
numSamp "17"
}
Block {
BlockType Reference
Name "M-FSK\nModulator\nBaseband"
Ports [1, 1]
Position [240, 75, 315, 125]
SourceBlock "commdigbbndfm2/M-FSK\nModulator\nBaseband"
SourceType "M-FSK Modulator Baseband"
M "2"
InType "Integer"
Enc "Binary"
freqSep "6"
phaseType "Continuous"
numSamp "17"
}
Line {
SrcBlock "Binary\nCyclic Encoder"
SrcPort 1
DstBlock "M-FSK\nModulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "M-FSK\nModulator\nBaseband"
SrcPort 1
DstBlock "AWGN\nChannel"
DstPort 1
}
Line {
SrcBlock "AWGN\nChannel"
SrcPort 1
DstBlock "M-FSK\nDemodulator\nBaseband"
DstPort 1
}
Line {
SrcBlock "M-FSK\nDemodulator\nBaseband"
SrcPort 1
Points [0, 105]
DstBlock "Binary\nCyclic Decoder"
DstPort 1
}
Line {
SrcBlock "Binary\nCyclic Decoder"
SrcPort 1
DstBlock "Error Rate\nCalculation"
DstPort 2
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Binary\nCyclic Encoder"
DstPort 1
}
Branch {
Points [0, 80]
DstBlock "Error Rate\nCalculation"
DstPort 1
}
}
}
}
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