.asg #6c00h, EBSR
	.asg #07fdh, SYSR
	.asg  	#0800h,EGCR
	.asg	#0801h,EMIRST
	.asg 	#0802h,EMIBE
	.asg 	#0803h,CE01
	.asg	#0804h,CE02
	.asg	#0805h,CE03
	.asg	#0806h,CE11
	.asg	#0807h,CE12
	.asg	#0808h,CE13
	.asg	#0809h,CE21
	.asg	#080ah,CE22
	.asg	#080bh,CE23
	.asg	#080ch,CE31
	.asg	#080dh,CE32
	.asg	#080eh,CE33
	.asg	#080fh,SDC1
	.asg	#0810h,SDPER
	.asg	#0811h,SDCNT
	.asg	#0812h,INIT
	.asg	#0813h,SDC2
	.asg	#0814h,SDC3
	.asg #3400h, IODIR      
	.asg #3401h, IODATA    
	.asg #0001h, ICR
	.asg #0002h, ISTR
	
	
	.text
.cpl_off_ke .macro 
	.cpl_off
	bit(st1,#14)= 0
	.endm
	
.cpl_on_ke .macro
	.cpl_on
	bit(st1, #14) = 1
	.endm 
  

	.def _initial_sys
_initial_sys: 
************ initial the state register *********************************	
  	*port(IODATA)= #1fh		
  	*port(IODIR) = #70h		
  	*port(IODATA)= #1fh   	
  							
  	bit(st1, #13) = #1		
   
	xar0=#0h
	nop
	ar0=#02h  			
	*ar0=#3800h
	ar0+=#1 			
	*ar0=#6100h 		
	xdp=#0       			
	
	ar0=*abs16(#01h)		
	ar0=*abs16(#46h)		

	bit(st1,#11)=#1
	bit(st1,#10)=#0 
	bit(st1,#7)=#0
	bit(st1,#9)=#0  
	bit(st1,#8)=#0

	
	xar0=#0
	nop
	*ar0=#0			
															

frequencySet_pll:
	ar3=#1c00h                                                
	*port(#1c00h) = #2610h 
again_pll_sub:                                               
	tc1=bit(*ar3,#0) || readport() 	
	if(!tc1) goto again_pll_sub                              
	*port(#7fdh)=#000b   
	*port(EBSR)=#9a01h 

	*port(ICR) = #002fh
	
	*port(SYSR)=#0000h
	*port(EMIRST)=#0ffffh  
	
	ar0=*port(EGCR)
	bit(ar0,@#5)=#0  
	*port(EGCR)=ar0
	
	ar0=*port(EGCR) 
	bit(ar0, @#9)=#1
	bit(ar0, @#10)=#0
	bit(ar0, @#11)=#0
	*port(EGCR)=ar0
	
	ar0=*port(EGCR)  
	bit(ar0, @#4)=#1
	*port(EGCR)=ar0
	

	repeat(#5)
	nop
	
	*port(CE01)=#1313h 
	*port(CE02)=#011bh
	*port(CE03)=#0000h		
	
	

	*port(CE11)=#151fh 
	*port(CE12)=#0f75fh
	*port(CE13)=#0000h
	
	*port(CE21)=#3000h
	*port(CE23)=#0000h
	*port(CE31)=#3000h
	*port(CE33)=#0000h
	*port(SDC1)=#2111h
	*port(SDPER)=#03e8h	
	*port(SDC2)=#0222h
	
	ar0=*port(SDC3) 
	bit(ar0, @#2)=#0
	*port(SDC3)=ar0
	
	ar0=*port(EGCR)  
	bit(ar0, @#5)=#1
	*port(EGCR)=ar0
	repeat(#20)
	nop_16
	
	*port(INIT)=#0000h
	repeat(#20)
	nop_16
***************************************************************
	ar0=#49h 
	*ar0=#0002h
	ar0+=#1
	*ar0=#0002h
	
	xar0=#0
	nop
	nop
	*ar0=#0
	
	ar1=*ar0
	bit(ar1,@#9)=#0 
	bit(ar1,@#4)=#0 
	*ar0=ar1
	
	ar0=#45h
	ar1=*ar0
	bit(ar1,@#3)=#0 
	bit(ar1,@#2)=#0 
	bit(ar1,@#4)=#0 
	bit(ar1,@#8)=#0
	*ar0=ar1
	

	.cpl_on_ke
	return