?? ml674000.h
字號(hào):
/********************************************************/
/***************** ML674000 H ************************/
/********************************************************/
//#ifndef ML674000_H
//#define ML674000_H
//#ifdef _cpluspus
//extern "c"{
//#endif
//external SRAM
#define SRAM_BASE (0xc8000000);Defined External SRAM
#define SRAM_SIZE (0x1FFF)
#define SRAM_TOP (SRAM_BASE+SRAM_TOP)
// Internal RAM
#define RAM_BASE (0x10000000)
#define RAM_SIZE (0X2000)
#define RAM_TOP (RAM_BASE+RAM_TOP)
// external ROM
#define FLASH_BASE (0xC8000000)
#define FLASH_SIZE (0x80000)
#define FLASH_TOP (FLASH_BASE+FLASH_SIZE)
//external SDRAM
#define SDRAM_BASE (0xC0000000) ;External SDRAM
#define SDRAM_SIZE (0x140000)
#define SDRAM_TOP (SDRAM_BASE+SDRAM_SIZE)
#define _ISR_STARTADDRESS 0xD001F000
#define Remap_Base (0xB8000001) ;address of map controller base
#define Romac_Base (0x78100004) ;address of flash controller base
#define Ramac_Base (0x78100008) ;address of ram controller base
#define GPCTL (* (volatile signed *) (0xB7000000))
#define BCKCTL_Base (0xB7000004)
/*******************************************************/
/* interrupt control register */
/*******************************************************/
#define ICR_BASE 0x78000000
#define IRQ (*(volatile unsigned *)(ICR_BASE+0x00))
#define IRQS (*(volatile unsigned *)(ICR_BASE+0x04))
#define FIQ (*(volatile unsigned *)(ICR_BASE+0x08))
#define FIQRAW (*(volatile unsigned *)(ICR_BASE+0x0C))
#define FIQEN (*(volatile unsigned *)(ICR_BASE+0X10))
#define IRN (*(volatile unsigned *)(ICR_BASE+0x14))
#define CIL (*(volatile unsigned *)(ICR_BASE+0x18))
#define ILC0 (*(volatile unsigned *)(ICR_BASE+0x20))
#define ILC1 (*(volatile unsigned *)(ICR_BASE+0x24))
#define CILCL (*(volatile unsigned *)(ICR_BASE+0x28))
#define CILE (*(volatile unsigned *)(ICR_BASE+0x2C))
/********************************************************/
/* external memory control register */
/********************************************************/
#define EMCR_BASE 0x78100000
#define BWC (*(volatile unsigned *)(EMCR_BASE+0x00))
#define ROMAC (*(volatile unsigned *)(EMCR_BASE+0x04))
#define RAMAC (*(volatile unsigned *)(EMCR_BASE+0x08))
#define IO0AC (*(volatile unsigned *)(EMCR_BASE+0x0c))
#define IO1AC (*(volatile unsigned *)(EMCR_BASE+0x10))
/********************************************************/
/*** SYSTEM CONTROL REGISTER */
/*******************************************************/
#define SCR_BASE 0xB8000000
#define IDR (*(volatile unsigned *)(SCR_BASE+0x00))
#define CLKSTP (*(volatile unsigned *)(SCR_BASE+0x04))
#define CGBCNT0 (*(volatile unsigned *)(SCR_BASE+0x08))
#define CKWT (*(volatile unsigned *)(SCR_BASE+0x0c))
#define RMPCON (*(volatile unsigned *)(SCR_BASE+0x10))
#define PST (*(volatile unsigned *)(SCR_BASE+0x14))
#define CGBCNT1 (*(volatile unsigned *)(SCR_BASE+0x18))
#define CGBCNT2 (*(volatile unsigned *)(SCR_BASE+0x1c))
/*********************************************************/
/* system timer control register */
/********************************************************/
#define STCR_BASE 0xB8001000
#define TMEN (*(volatile unsigned *)(STCR_BASE+0x04))
#define TMRLR (*(volatile unsigned *)(STCR_BASE+0x08))
#define TMOVFR (*(volatile unsigned *)(STCR_BASE+0x10))
#define TMEN_TCEN 0x01
#define TMOVF_OVF 0x01
/**********************************************************/
/* SIO CONTROL REGISTER */
/**********************************************************/
#define SIOCR_BASE 0xB8002000
#define SIOBUF (*(volatile unsigned *)(SIOCR_BASE+0x00))
#define SIOSTA (*(volatile unsigned *)(SIOCR_BASE+0x04))
#define SIOCON (*(volatile unsigned *)(SIOCR_BASE+0x08))
#define SIOBCN (*(volatile unsigned *)(SIOCR_BASE+0x0c))
#define SIOBT (*(volatile unsigned *)(SIOCR_BASE+0x14))
#define SIOTCN (*(volatile unsigned *)(SIOCR_BASE+0x18))
/***************************************************************/
/* timer control register */
/**************************************************************/
#define TCR_BASE 0xB7F00000
#define TIMECNTL0 (*(volatile unsigned *)(TCR_BASE+0x00))
#define TIMEBASE0 (*(volatile unsigned *)(TCR_BASE+0x04))
#define TIMECNT0 (*(volatile unsigned *)(TCR_BASE+0x08))
#define TIMECMP0 (*(volatile unsigned *)(TCR_BASE+0x0C))
#define TIMESTAT0 (*(volatile unsigned *)(TCR_BASE+0x10))
#define TIMECNTL1 (*(volatile unsigned *)(TCR_BASE+0x20))
#define TIMEBASE1 (*(volatile unsigned *)(TCR_BASE+0x24))
#define TIMECNT1 (*(volatile unsigned *)(TCR_BASE+0x28))
#define TIMECMP1 (*(volatile unsigned *)(TCR_BASE+0x2c))
#define TIMESTAT1 (*(volatile unsigned *)(TCR_BASE+0x30))
#define TIMECNTL2 (*(volatile unsigned *)(TCR_BASE+0x40))
#define TIMEBASE2 (*(volatile unsigned *)(TCR_BASE+0x44))
#define TIMECNT2 (*(volatile unsigned *)(TCR_BASE+0x48))
#define TIMECMP2 (*(volatile unsigned *)(TCR_BASE+0x4c))
#define TIMESTAT2 (*(volatile unsigned *)(TCR_BASE+0x50))
#define TIMECNTL3 (*(volatile unsigned *)(TCR_BASE+0x60))
#define TIMEBASE3 (*(volatile unsigned *)(TCR_BASE+0x64))
#define TIMECNT3 (*(volatile unsigned *)(TCR_BASE+0x68))
#define TIMECMP3 (*(volatile unsigned *)(TCR_BASE+0x6c))
#define TIMESTAT3 (*(volatile unsigned *)(TCR_BASE+0x70))
#define TIMECNTL4 (*(volatile unsigned *)(TCR_BASE+0x80))
#define TIMEBASE4 (*(volatile unsigned *)(TCR_BASE+0x84))
#define TIMECNT4 (*(volatile unsigned *)(TCR_BASE+0x88))
#define TIMECMP4 (*(volatile unsigned *)(TCR_BASE+0x8c))
#define TIMESTAT4 (*(volatile unsigned *)(TCR_BASE+0x90))
#define TIMECNTL5 (*(volatile unsigned *)(TCR_BASE+0xa0))
#define TIMENASE5 (*(volatile unsigned *)(TCR_BASE+0xa4))
#define TIMCNT5 (*(volatile unsigned *)(TCR_BASE+0xa8))
#define TIMECMP5 (*(volatile unsigned *)(TCR_BASE+0xac))
#define TIMESTAT5 (*(volatile unsigned *)(TCR_BASE+0xb0))
/**************************************************/
/* GPIO control register */
/***************************************************/
#define GPIO_BASE 0xB7A00000
#define GPP0A (*(volatile unsigned *)(GPIO_BASE+0x00))
#define GPP1A (*(volatile unsigned *)(GPIO_BASE+0X04))
#define GPPMA (*(volatile unsigned *)(GPIO_BASE+0x08))
#define GP1EA (*(volatile unsigned *)(GPIO_BASE+0x0C))
#define GP1PA (*(volatile unsigned *)(GPIO_BASE+0x10))
#define GP1SA (*(volatile unsigned *)(GPIO_BASE+0x14))
#define PA0 (1<<0)
#define PA1 (1<<1)
#define PA2 (1<<2)
#define PA3 (1<<3)
#define PA4 (1<<4)
#define PA5 (1<<5)
#define PA6 (1<<6)
#define PA7 (1<<7)
#define PA8 (1<<8)
#define PA9 (1<<9)
#define PA10 (1<<10)
#define PA11 (1<<11)
#define PA12 (1<<12)
#define PA13 (1<<13)
#define PA14 (1<<14)
#define PA15 (1<<15)
#define GPP0B (*(volatile unsigned *)(GPIO_BASE+0x20))
#define GPP1B (*(volatile unsigned *)(GPIO_BASE+0x24))
#define GPPMB (*(volatile unsigned *)(GPIO_BASE+0x28))
#define GP1EB (*(volatile unsigned *)(GPIO_BASE+0x2C))
#define GPIPB (*(volatile unsigned *)(GPIO_BASE+0x30))
#define GP1SB (*(volatile unsigned *)(GPIO_BASE+0x34))
#define PB0 (1<<0)
#define PB1 (1<<1)
#define PB2 (1<<2)
#define PB3 (1<<3)
#define PB4 (1<<4)
#define PB5 (1<<5)
#define PB6 (1<<6)
#define PB7 (1<<7)
#define PB8 (1<<8)
#define PB9 (1<<9)
#define PB10 (1<<10)
#define PB11 (1<<11)
#define PB12 (1<<12)
#define PB13 (1<<13)
#define PB14 (1<<14)
#define PB15 (1<<15)
#define Mode_USR 0x10
#define Mode_IRQ 0x12
#define Mode_SVC 0x13
#define Mode_SYS 0x1F
#define I_Bit 0x80
#define F_Bit 0x40
#define SWI_IRQ_EN 0x00 // SWI number of irq_en
#define SWI_IRQ_DIS 0x01 // ; SWI number of irq_dis
#define USR_SWI_MAX 0x01 //; maximum user SWI number
//////////////////////////////////////////////////////////////////////
//define WDTCON
#define WDTBCON (*(volatile unsigned *)0xB7E00000)
#define WDSTAT (*(volatile unsigned *)0xB7E00014)
#define WDTCON (*(volatile unsigned *)0XB7E00000)
///UART
#define UCR_BASE 0xB7B00000 /* base address */
#define UARTRBR (*(volatile unsigned *)(UCR_BASE+0x00)) /* receiver buffer register */
#define UARTTHR (*(volatile unsigned *)(UCR_BASE+0x00))/* transmitter buffer register */
#define UARTIER (*(volatile unsigned *)(UCR_BASE+0x04))/* interrupt enable register */
#define UARTIIR (*(volatile unsigned *)(UCR_BASE+0x08)) /* interrupt identification */
#define UARTFCR (*(volatile unsigned *)(UCR_BASE+0x08))/* FIFO control register */
#define UARTLCR (*(volatile unsigned *)(UCR_BASE+0x0C)) /* line control register */
#define UARTMCR (*(volatile unsigned *)(UCR_BASE+0x10)) /* modem control register */
#define UARTLSR (*(volatile unsigned *)(UCR_BASE+0x14)) /* line status register */
#define UARTMSR (*(volatile unsigned *)(UCR_BASE+0x18)) /* modem status register */
#define UARTSCR (*(volatile unsigned *)(UCR_BASE+0x1C)) /* scratchpad register */
#define UARTDLL (*(volatile unsigned *)(UCR_BASE+0x00)) /* divisor latch(LSB) */
#define UARTDLM (*(volatile unsigned *)(UCR_BASE+0x04)) /* divisor latch(MSB) */
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