/*=============================================================================*/
/* File Name : s3c2410.h*/
/* Function  : S3C2410 Define Address Register*/
/* Program   : Shin, On Pil (SOP)*/
/* Date      : May 06, 2002*/
/* Version   : 0.0*/
/* History*/
/*   0.0 : Programming start (February 15,2002) -> SOP*/
/*         INTERRUPT rPRIORITY 0x4a00000a -> 0x4a00000c       (May 02, 2002 SOP)*/
/*         RTC BCD DAY and DATE Register Name Correction      (May 06, 2002 SOP) */
/*=============================================================================*/

#ifndef __2410_H__
#define __2410_H__

#ifdef __cplusplus
extern "C" {
#endif
/*option*/
#define _RAM_STARTADDRESS       0x30000000 
#define _NONCACHE_STARTADDRESS	0x31000000 
 
#define _ISR_STARTADDRESS       0x33ffff00 
      
#define _MMUTT_STARTADDRESS     0x33ff8000 
 
#define _STACK_BASEADDRESS      0x33ff8000 
 
#define HEAPEND                 0x33ff0000 

/* Memory control */
#define rBWSCON    (*(volatile unsigned *)0x48000000) /*Bus width & wait status*/
#define rBANKCON0  (*(volatile unsigned *)0x48000004) /*Boot ROM control*/
#define rBANKCON1  (*(volatile unsigned *)0x48000008) /*BANK1 control*/
#define rBANKCON2  (*(volatile unsigned *)0x4800000c) /*BANK2 cControl*/
#define rBANKCON3  (*(volatile unsigned *)0x48000010) /*BANK3 control*/
#define rBANKCON4  (*(volatile unsigned *)0x48000014) /*BANK4 control*/
#define rBANKCON5  (*(volatile unsigned *)0x48000018) /*BANK5 control*/
#define rBANKCON6  (*(volatile unsigned *)0x4800001c) /*BANK6 control*/
#define rBANKCON7  (*(volatile unsigned *)0x48000020) /*BANK7 control*/
#define rREFRESH   (*(volatile unsigned *)0x48000024) /*DRAM/SDRAM refresh*/
#define rBANKSIZE  (*(volatile unsigned *)0x48000028) /*Flexible Bank Size*/
#define rMRSRB6    (*(volatile unsigned *)0x4800002c) /*Mode register set for SDRAM*/
#define rMRSRB7    (*(volatile unsigned *)0x48000030) /*Mode register set for SDRAM*/


/* USB Host*/


/* INTERRUPT*/
#define rSRCPND     (*(volatile unsigned *)0x4a000000) /*Interrupt request status*/
#define rINTMOD     (*(volatile unsigned *)0x4a000004) /*Interrupt mode control*/
#define rINTMSK     (*(volatile unsigned *)0x4a000008) /*Interrupt mask control*/
#define rPRIORITY   (*(volatile unsigned *)0x4a00000c) /*IRQ priority control*/
#define rINTPND     (*(volatile unsigned *)0x4a000010) /*Interrupt request status*/
#define rINTOFFSET  (*(volatile unsigned *)0x4a000014) /*Interruot request source offset*/
#define rSUBSRCPND  (*(volatile unsigned *)0x4a000018) /*Sub source pending*/
#define rINTSUBMSK  (*(volatile unsigned *)0x4a00001c) /*Interrupt sub mask*/


/* DMA*/
#define rDISRC0     (*(volatile unsigned *)0x4b000000) /*DMA 0 Initial source*/
#define rDISRCC0    (*(volatile unsigned *)0x4b000004) /*DMA 0 Initial source control*/
#define rDIDST0     (*(volatile unsigned *)0x4b000008) /*DMA 0 Initial Destination*/
#define rDIDSTC0    (*(volatile unsigned *)0x4b00000c) /*DMA 0 Initial Destination control*/
#define rDCON0      (*(volatile unsigned *)0x4b000010) /*DMA 0 Control*/
#define rDSTAT0     (*(volatile unsigned *)0x4b000014) /*DMA 0 Status*/
#define rDCSRC0     (*(volatile unsigned *)0x4b000018) /*DMA 0 Current source*/
#define rDCDST0     (*(volatile unsigned *)0x4b00001c) /*DMA 0 Current destination*/
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) /*DMA 0 Mask trigger*/

#define rDISRC1     (*(volatile unsigned *)0x4b000040) /*DMA 1 Initial source*/
#define rDISRCC1    (*(volatile unsigned *)0x4b000044) /*DMA 1 Initial source control*/
#define rDIDST1     (*(volatile unsigned *)0x4b000048) /*DMA 1 Initial Destination*/
#define rDIDSTC1    (*(volatile unsigned *)0x4b00004c) /*DMA 1 Initial Destination control*/
#define rDCON1      (*(volatile unsigned *)0x4b000050) /*DMA 1 Control*/
#define rDSTAT1     (*(volatile unsigned *)0x4b000054) /*DMA 1 Status*/
#define rDCSRC1     (*(volatile unsigned *)0x4b000058) /*DMA 1 Current source*/
#define rDCDST1     (*(volatile unsigned *)0x4b00005c) /*DMA 1 Current destination*/
#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) /*DMA 1 Mask trigger*/

#define rDISRC2     (*(volatile unsigned *)0x4b000080) /*DMA 2 Initial source*/
#define rDISRCC2    (*(volatile unsigned *)0x4b000084) /*DMA 2 Initial source control*/
#define rDIDST2     (*(volatile unsigned *)0x4b000088) /*DMA 2 Initial Destination*/
#define rDIDSTC2    (*(volatile unsigned *)0x4b00008c) /*DMA 2 Initial Destination control*/
#define rDCON2      (*(volatile unsigned *)0x4b000090) /*DMA 2 Control*/
#define rDSTAT2     (*(volatile unsigned *)0x4b000094) /*DMA 2 Status*/
#define rDCSRC2     (*(volatile unsigned *)0x4b000098) /*DMA 2 Current source*/
#define rDCDST2     (*(volatile unsigned *)0x4b00009c) /*DMA 2 Current destination*/
#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) /*DMA 2 Mask trigger*/

#define rDISRC3     (*(volatile unsigned *)0x4b0000c0) /*DMA 3 Initial source*/
#define rDISRCC3    (*(volatile unsigned *)0x4b0000c4) /*DMA 3 Initial source control*/
#define rDIDST3     (*(volatile unsigned *)0x4b0000c8) /*DMA 3 Initial Destination*/
#define rDIDSTC3    (*(volatile unsigned *)0x4b0000cc) /*DMA 3 Initial Destination control*/
#define rDCON3      (*(volatile unsigned *)0x4b0000d0) /*DMA 3 Control*/
#define rDSTAT3     (*(volatile unsigned *)0x4b0000d4) /*DMA 3 Status*/
#define rDCSRC3     (*(volatile unsigned *)0x4b0000d8) /*DMA 3 Current source*/
#define rDCDST3     (*(volatile unsigned *)0x4b0000dc) /*DMA 3 Current destination*/
#define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) /*DMA 3 Mask trigger*/


/* CLOCK & POWER MANAGEMENT*/
#define rLOCKTIME   (*(volatile unsigned *)0x4c000000) /*PLL lock time counter*/
#define rMPLLCON    (*(volatile unsigned *)0x4c000004) /*MPLL Control*/
#define rUPLLCON    (*(volatile unsigned *)0x4c000008) /*UPLL Control*/
#define rCLKCON     (*(volatile unsigned *)0x4c00000c) /*Clock generator control*/
#define rCLKSLOW    (*(volatile unsigned *)0x4c000010) /*Slow clock control*/
#define rCLKDIVN    (*(volatile unsigned *)0x4c000014) /*Clock divider control*/


/* LCD CONTROLLER*/
#define rLCDCON1    (*(volatile unsigned *)0x4d000000) /*LCD control 1*/
#define rLCDCON2    (*(volatile unsigned *)0x4d000004) /*LCD control 2*/
#define rLCDCON3    (*(volatile unsigned *)0x4d000008) /*LCD control 3*/
#define rLCDCON4    (*(volatile unsigned *)0x4d00000c) /*LCD control 4*/
#define rLCDCON5    (*(volatile unsigned *)0x4d000010) /*LCD control 5*/
#define rLCDSADDR1  (*(volatile unsigned *)0x4d000014) /*STN/TFT Frame buffer start address 1*/
#define rLCDSADDR2  (*(volatile unsigned *)0x4d000018) /*STN/TFT Frame buffer start address 2*/
#define rLCDSADDR3  (*(volatile unsigned *)0x4d00001c) /*STN/TFT Virtual screen address set*/
#define rREDLUT     (*(volatile unsigned *)0x4d000020) /*STN Red lookup table*/
#define rGREENLUT   (*(volatile unsigned *)0x4d000024) /*STN Green lookup table*/ 
#define rBLUELUT    (*(volatile unsigned *)0x4d000028) /*STN Blue lookup table*/
#define rDITHMODE   (*(volatile unsigned *)0x4d00004c) /*STN Dithering mode*/
#define rTPAL       (*(volatile unsigned *)0x4d000050) /*TFT Temporary palette*/
#define rLCDINTPND  (*(volatile unsigned *)0x4d000054) /*LCD Interrupt pending*/
#define rLCDSRCPND  (*(volatile unsigned *)0x4d000058) /*LCD Interrupt source*/
#define rLCDINTMSK  (*(volatile unsigned *)0x4d00005c) /*LCD Interrupt mask*/
#define rLPCSEL     (*(volatile unsigned *)0x4d000060) /*LPC3600 Control*/
#define PALETTE     0x4d000400                         /*Palette start address*/


/* NAND flash*/
#define rNFCONF     (*(volatile unsigned *)0x4e000000)      /*NAND Flash configuration*/
#define rNFCMD      (*(volatile UCHAR *)0x4e000004)            /*NADD Flash command*/
#define rNFADDR     (*(volatile UCHAR *)0x4e000008)            /*NAND Flash address*/
#define rNFDATA     (*(volatile UCHAR *)0x4e00000c)            /*NAND Flash data*/
#define rNFSTAT     (*(volatile unsigned *)0x4e000010)      /*NAND Flash operation status*/
#define rNFECC      (*(volatile unsigned *)0x4e000014)      /*NAND Flash ECC*/
#define rNFECC0     (*(volatile UCHAR  *)0x4e000014)
#define rNFECC1     (*(volatile UCHAR  *)0x4e000015)
#define rNFECC2     (*(volatile UCHAR  *)0x4e000016)

/* UART*/
#define rULCONx(ch)   (*(volatile unsigned *)(0x50000000+(ch<<14))) //UART x Line control
#define rUCONx(ch)    (*(volatile unsigned *)(0x50000004+(ch<<14))) //UART x Control
#define rUFCONx(ch)   (*(volatile unsigned *)(0x50000008+(ch<<14))) //UART x FIFO control
#define rUMCONx(ch)   (*(volatile unsigned *)(0x5000000c+(ch<<14))) //UART x Modem control
#define rUTRSTATx(ch) (*(volatile unsigned *)(0x50000010+(ch<<14))) //UART x Tx/Rx status
#define rUERSTATx(ch) (*(volatile unsigned *)(0x50000014+(ch<<14))) //UART x Rx error status
#define rUFSTATx(ch)  (*(volatile unsigned *)(0x50000018+(ch<<14))) //UART x FIFO status
#define rUMSTATx(ch)  (*(volatile unsigned *)(0x5000001c+(ch<<14))) //UART x Modem status
#define rUBRDIVx(ch)  (*(volatile unsigned *)(0x50000028+(ch<<14))) //UART x Baud rate divisor

#define aULCON0	   0x50000000
#define rULCON0     (*(volatile unsigned *)0x50000000) /*UART 0 Line control*/
#define rUCON0      (*(volatile unsigned *)0x50000004) /*UART 0 Control*/
#define rUFCON0     (*(volatile unsigned *)0x50000008) /*UART 0 FIFO control*/
#define rUMCON0     (*(volatile unsigned *)0x5000000c) /*UART 0 Modem control*/
#define rUTRSTAT0   (*(volatile unsigned *)0x50000010) /*UART 0 Tx/Rx status*/
#define rUERSTAT0   (*(volatile unsigned *)0x50000014) /*UART 0 Rx error status*/
#define rUFSTAT0    (*(volatile unsigned *)0x50000018) /*UART 0 FIFO status*/
#define rUMSTAT0    (*(volatile unsigned *)0x5000001c) /*UART 0 Modem status*/
#define rUBRDIV0    (*(volatile unsigned *)0x50000028) /*UART 0 Baud rate divisor*/

#define aULCON1	   0x50004000
#define rULCON1     (*(volatile unsigned *)0x50004000) /*UART 1 Line control*/
#define rUCON1      (*(volatile unsigned *)0x50004004) /*UART 1 Control*/
#define rUFCON1     (*(volatile unsigned *)0x50004008) /*UART 1 FIFO control*/
#define rUMCON1     (*(volatile unsigned *)0x5000400c) /*UART 1 Modem control*/
#define rUTRSTAT1   (*(volatile unsigned *)0x50004010) /*UART 1 Tx/Rx status*/
#define rUERSTAT1   (*(volatile unsigned *)0x50004014) /*UART 1 Rx error status*/
#define rUFSTAT1    (*(volatile unsigned *)0x50004018) /*UART 1 FIFO status*/
#define rUMSTAT1    (*(volatile unsigned *)0x5000401c) /*UART 1 Modem status*/
#define rUBRDIV1    (*(volatile unsigned *)0x50004028) /*UART 1 Baud rate divisor*/

#define aULCON2	   0x50008000
#define rULCON2     (*(volatile unsigned *)0x50008000) /*UART 2 Line control*/
#define rUCON2      (*(volatile unsigned *)0x50008004) /*UART 2 Control*/
#define rUFCON2     (*(volatile unsigned *)0x50008008) /*UART 2 FIFO control*/
#define rUMCON2     (*(volatile unsigned *)0x5000800c) /*UART 2 Modem control*/
#define rUTRSTAT2   (*(volatile unsigned *)0x50008010) /*UART 2 Tx/Rx status*/
#define rUERSTAT2   (*(volatile unsigned *)0x50008014) /*UART 2 Rx error status*/
#define rUFSTAT2    (*(volatile unsigned *)0x50008018) /*UART 2 FIFO status*/
#define rUMSTAT2    (*(volatile unsigned *)0x5000801c) /*UART 2 Modem status*/
#define rUBRDIV2    (*(volatile unsigned *)0x50008028) /*UART 2 Baud rate divisor*/

#ifdef __BIG_ENDIAN
#define rUTXH0      (*(volatile unsigned char *)0x50000023) /*UART 0 Transmission Hold*/
#define rURXH0      (*(volatile unsigned char *)0x50000027) /*UART 0 Receive buffer*/
#define rUTXH1      (*(volatile unsigned char *)0x50004023) /*UART 1 Transmission Hold*/
#define rURXH1      (*(volatile unsigned char *)0x50004027) /*UART 1 Receive buffer*/
#define rUTXH2      (*(volatile unsigned char *)0x50008023) /*UART 2 Transmission Hold*/
#define rURXH2      (*(volatile unsigned char *)0x50008027) /*UART 2 Receive buffer*/

#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0x50000027)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0x50004027)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0x50008027)

#define UTXH0       (0x50000020+3)  /*Byte_access address by DMA*/
#define URXH0       (0x50000024+3)
#define UTXH1       (0x50004020+3)
#define URXH1       (0x50004024+3)
#define UTXH2       (0x50008020+3)
#define URXH2       (0x50008024+3)

#else /*Little Endian*/
#define rUTXHx(ch)  (*(volatile unsigned char *)(0x50000020+(ch<<14))) //UART x Transmission Hold
#define RdURXHx(ch) (*(volatile unsigned char *)(0x50000024+(ch<<14)))

#define rUTXH0 (*(volatile unsigned char *)0x50000020) /*UART 0 Transmission Hold*/
#define rURXH0 (*(volatile unsigned char *)0x50000024) /*UART 0 Receive buffer*/
#define rUTXH1 (*(volatile unsigned char *)0x50004020) /*UART 1 Transmission Hold*/
#define rURXH1 (*(volatile unsigned char *)0x50004024) /*UART 1 Receive buffer*/
#define rUTXH2 (*(volatile unsigned char *)0x50008020) /*UART 2 Transmission Hold*/
#define rURXH2 (*(volatile unsigned char *)0x50008024) /*UART 2 Receive buffer*/

#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
#define RdURXH0()   (*(volatile unsigned char *)0x50000024)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
#define RdURXH1()   (*(volatile unsigned char *)0x50004024)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
#define RdURXH2()   (*(volatile unsigned char *)0x50008024)

#define UTXH0       (0x50000020)    /*Byte_access address by DMA*/
#define URXH0       (0x50000024)
#define UTXH1       (0x50004020)
#define URXH1       (0x50004024)
#define UTXH2       (0x50008020)
#define URXH2       (0x50008024)
#endif


/* PWM TIMER*/
#define rTCFG0  (*(volatile unsigned *)0x51000000) /*Timer 0 configuration*/
#define rTCFG1  (*(volatile unsigned *)0x51000004) /*Timer 1 configuration*/
#define rTCON   (*(volatile unsigned *)0x51000008) /*Timer control*/
#define rTCNTB0 (*(volatile unsigned *)0x5100000c) /*Timer count buffer 0*/
#define rTCMPB0 (*(volatile unsigned *)0x51000010) /*Timer compare buffer 0*/
#define rTCNTO0 (*(volatile unsigned *)0x51000014) /*Timer count observation 0*/
#define rTCNTB1 (*(volatile unsigned *)0x51000018) /*Timer count buffer 1*/
#define rTCMPB1 (*(volatile unsigned *)0x5100001c) /*Timer compare buffer 1*/
#define rTCNTO1 (*(volatile unsigned *)0x51000020) /*Timer count observation 1*/
#define rTCNTB2 (*(volatile unsigned *)0x51000024) /*Timer count buffer 2*/
#define rTCMPB2 (*(volatile unsigned *)0x51000028) /*Timer compare buffer 2*/
#define rTCNTO2 (*(volatile unsigned *)0x5100002c) /*Timer count observation 2*/
#define rTCNTB3 (*(volatile unsigned *)0x51000030) /*Timer count buffer 3*/
#define rTCMPB3 (*(volatile unsigned *)0x51000034) /*Timer compare buffer 3*/
#define rTCNTO3 (*(volatile unsigned *)0x51000038) /*Timer count observation 3*/
#define rTCNTB4 (*(volatile unsigned *)0x5100003c) /*Timer count buffer 4*/
#define rTCNTO4 (*(volatile unsigned *)0x51000040) /*Timer count observation 4*/


/* USB DEVICE*/
#ifdef __BIG_ENDIAN
<ERROR IF BIG_ENDIAN>
#define rFUNC_ADDR_REG     (*(volatile unsigned char *)0x52000143) /*Function address*/
#define rPWR_REG           (*(volatile unsigned char *)0x52000147) /*Power management*/
#define rEP_INT_REG        (*(volatile unsigned char *)0x5200014b) /*EP Interrupt pending and clear*/