# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		huang_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY ACEX1K
set_global_assignment -name DEVICE "EP1K30QC208-3"
set_global_assignment -name TOP_LEVEL_ENTITY huang
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:10:10  MAY 15, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name VERILOG_FILE huang.v
set_location_assignment PIN_79 -to clk
set_location_assignment PIN_169 -to led[7]
set_location_assignment PIN_170 -to led[6]
set_location_assignment PIN_172 -to led[5]
set_location_assignment PIN_173 -to led[4]
set_location_assignment PIN_160 -to led[3]
set_location_assignment PIN_163 -to led[2]
set_location_assignment PIN_167 -to led[1]
set_location_assignment PIN_168 -to led[0]
set_location_assignment PIN_60 -to led_dig[7]
set_location_assignment PIN_39 -to led_dig[6]
set_location_assignment PIN_37 -to led_dig[5]
set_location_assignment PIN_56 -to led_dig[4]
set_location_assignment PIN_61 -to led_dig[3]
set_location_assignment PIN_58 -to led_dig[2]
set_location_assignment PIN_55 -to led_dig[1]
set_location_assignment PIN_57 -to led_dig[0]
set_location_assignment PIN_67 -to led_seg[7]
set_location_assignment PIN_65 -to led_seg[6]
set_location_assignment PIN_64 -to led_seg[5]
set_location_assignment PIN_63 -to led_seg[4]
set_location_assignment PIN_68 -to led_seg[3]
set_location_assignment PIN_69 -to led_seg[2]
set_location_assignment PIN_70 -to led_seg[1]
set_location_assignment PIN_71 -to led_seg[0]
set_location_assignment PIN_174 -to reset