?? huang.vho
字號:
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"
-- DATE "05/15/2009 16:13:32"
--
-- Device: Altera EP1K30QC208-3 Package PQFP208
--
--
-- This VHDL file should be used for PRIMETIME only
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY huang IS
PORT (
clk : IN std_logic;
led_seg : OUT std_logic_vector(7 DOWNTO 0);
led_dig : OUT std_logic_vector(7 DOWNTO 0);
led : OUT std_logic_vector(7 DOWNTO 0);
reset : IN std_logic
);
END huang;
ARCHITECTURE structure OF huang IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_led_seg : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_led_dig : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_led : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_reset : std_logic;
SIGNAL \WideOr7~23_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr7~23_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector9~36_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector9~36_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Selector22~36_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Selector22~36_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~204_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~204_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~205_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~205_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[16]~321_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod0|auto_generated|divider|divider|StageOut[16]~321_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[16]~252_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod3|auto_generated|divider|divider|StageOut[16]~252_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_4|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ge_left~3178_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \ge_left~3178_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|add_sub_3|add_sub_cella[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[16]~331_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Mod2|auto_generated|divider|divider|StageOut[16]~331_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add1|adder|result_node|cs_buffer[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div1|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \shi_right~821_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \shi_right~821_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div3|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div0|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Div2|auto_generated|divider|divider|add_sub_3|add_sub_cella[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[23]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[23]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[20]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[20]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[22]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[22]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[21]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[21]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~231_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~231_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[19]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[19]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[18]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[18]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[17]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[17]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \cout[16]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \cout[16]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~232_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~232_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal0~235_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal0~235_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add2|adder|unreg_res_node[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add2|adder|unreg_res_node[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[16]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[16]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[15]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[15]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[14]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[14]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[13]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[13]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~212_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~212_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[20]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[20]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[19]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[19]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[18]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[18]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[17]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[17]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Equal1~216_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Equal1~216_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[8]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[8]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \couta[7]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \couta[7]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
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