{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 15 16:13:06 2009 " "Info: Processing started: Fri May 15 16:13:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off huang -c huang " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off huang -c huang" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "huang.v(130) " "Warning (10268): Verilog HDL information at huang.v(130): Always Construct contains both blocking and non-blocking assignments" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 130 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "huang.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file huang.v" { { "Info" "ISGN_ENTITY_NAME" "1 huang " "Info: Found entity 1: huang" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "huang " "Info: Elaborating entity \"huang\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 huang.v(35) " "Warning (10230): Verilog HDL assignment warning at huang.v(35): truncated value with size 32 to match size of target (24)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 21 huang.v(48) " "Warning (10230): Verilog HDL assignment warning at huang.v(48): truncated value with size 32 to match size of target (21)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 huang.v(60) " "Warning (10230): Verilog HDL assignment warning at huang.v(60): truncated value with size 32 to match size of target (6)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 huang.v(67) " "Warning (10230): Verilog HDL assignment warning at huang.v(67): truncated value with size 32 to match size of target (2)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(138) " "Warning (10230): Verilog HDL assignment warning at huang.v(138): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(139) " "Warning (10230): Verilog HDL assignment warning at huang.v(139): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 139 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(140) " "Warning (10230): Verilog HDL assignment warning at huang.v(140): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 140 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(142) " "Warning (10230): Verilog HDL assignment warning at huang.v(142): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(143) " "Warning (10230): Verilog HDL assignment warning at huang.v(143): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(144) " "Warning (10230): Verilog HDL assignment warning at huang.v(144): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 144 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(150) " "Warning (10230): Verilog HDL assignment warning at huang.v(150): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(152) " "Warning (10230): Verilog HDL assignment warning at huang.v(152): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 152 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(155) " "Warning (10230): Verilog HDL assignment warning at huang.v(155): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 155 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(161) " "Warning (10230): Verilog HDL assignment warning at huang.v(161): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(162) " "Warning (10230): Verilog HDL assignment warning at huang.v(162): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(163) " "Warning (10230): Verilog HDL assignment warning at huang.v(163): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(165) " "Warning (10230): Verilog HDL assignment warning at huang.v(165): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(166) " "Warning (10230): Verilog HDL assignment warning at huang.v(166): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}