{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(167) " "Warning (10230): Verilog HDL assignment warning at huang.v(167): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 huang.v(174) " "Warning (10230): Verilog HDL assignment warning at huang.v(174): truncated value with size 32 to match size of target (5)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(176) " "Warning (10230): Verilog HDL assignment warning at huang.v(176): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 huang.v(179) " "Warning (10230): Verilog HDL assignment warning at huang.v(179): truncated value with size 32 to match size of target (4)" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 179 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "led_dig\[7\]~reg0 High " "Info: Power-up level of register \"led_dig\[7\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_dig\[7\]~reg0 data_in VCC " "Warning: Reduced register \"led_dig\[7\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "led_dig\[6\]~reg0 High " "Info: Power-up level of register \"led_dig\[6\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_dig\[6\]~reg0 data_in VCC " "Warning: Reduced register \"led_dig\[6\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "led_dig\[3\]~reg0 High " "Info: Power-up level of register \"led_dig\[3\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_dig\[3\]~reg0 data_in VCC " "Warning: Reduced register \"led_dig\[3\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "led_dig\[2\]~reg0 High " "Info: Power-up level of register \"led_dig\[2\]~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led_dig\[2\]~reg0 data_in VCC " "Warning: Reduced register \"led_dig\[2\]~reg0\" with stuck data_in port to stuck value VCC" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led\[3\]~reg0 data_in GND " "Warning: Reduced register \"led\[3\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "led\[4\]~reg0 data_in GND " "Warning: Reduced register \"led\[4\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div2 " "Info: Elaborated megafunction instantiation \"lpm_divide:Div2\"" {  } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 162 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ovl.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ovl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ovl " "Info: Found entity 1: lpm_divide_ovl" {  } { { "db/lpm_divide_ovl.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/lpm_divide_ovl.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_4kh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_4kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_4kh " "Info: Found entity 1: sign_div_unsign_4kh" {  } { { "db/sign_div_unsign_4kh.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/sign_div_unsign_4kh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_cie.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_cie.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_cie " "Info: Found entity 1: alt_u_div_cie" {  } { { "db/alt_u_div_cie.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/alt_u_div_cie.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_j7c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_j7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_j7c " "Info: Found entity 1: add_sub_j7c" {  } { { "db/add_sub_j7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_j7c.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_k7c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_k7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_k7c " "Info: Found entity 1: add_sub_k7c" {  } { { "db/add_sub_k7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_k7c.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_l7c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_l7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_l7c " "Info: Found entity 1: add_sub_l7c" {  } { { "db/add_sub_l7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_l7c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_m7c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_m7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_m7c " "Info: Found entity 1: add_sub_m7c" {  } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_n7c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_n7c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_n7c " "Info: Found entity 1: add_sub_n7c" {  } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}