?? huang.map.qmsg
字號:
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add1 " "Info: Instantiated megafunction \"lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 21 " "Info: Parameter \"LPM_WIDTH\" = \"21\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 48 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|altshift:result_ext_latency_ffs lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 48 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add1 " "Info: Instantiated megafunction \"lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 21 " "Info: Parameter \"LPM_WIDTH\" = \"21\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 48 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Info: Parameter \"LPM_WIDTH\" = \"24\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Info: Parameter \"LPM_WIDTH\" = \"24\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Info: Parameter \"LPM_WIDTH\" = \"24\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" { } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add0 " "Info: Instantiated megafunction \"lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 24 " "Info: Parameter \"LPM_WIDTH\" = \"24\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 35 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "shi_right\[2\] shi_left\[2\] " "Info: Duplicate register \"shi_right\[2\]\" merged to single register \"shi_left\[2\]\"" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shi_right\[3\] shi_left\[2\] " "Info: Duplicate register \"shi_right\[3\]\" merged to single register \"shi_left\[2\]\"" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shi_left\[3\] shi_left\[2\] " "Info: Duplicate register \"shi_left\[3\]\" merged to single register \"shi_left\[2\]\"" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} } { } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "shi_left\[2\] data_in GND " "Warning: Reduced register \"shi_left\[2\]\" with stuck data_in port to stuck value GND" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led_dig\[2\] VCC " "Warning: Pin \"led_dig\[2\]\" stuck at VCC" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led_dig\[3\] VCC " "Warning: Pin \"led_dig\[3\]\" stuck at VCC" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led_dig\[6\] VCC " "Warning: Pin \"led_dig\[6\]\" stuck at VCC" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led_dig\[7\] VCC " "Warning: Pin \"led_dig\[7\]\" stuck at VCC" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 128 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[3\] GND " "Warning: Pin \"led\[3\]\" stuck at GND" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[4\] GND " "Warning: Pin \"led\[4\]\" stuck at GND" { } { { "huang.v" "" { Text "F:/verilog/實驗三操作/huang/huang.v" 188 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WFTM_IGNORED_UNIMPLEMENTABLE_CARRY" "6 " "Warning: Ignored 6 CARRY_SUM primitives" { { "Warning" "WFTM_CARRY_MERGE_FANIN_HDR" "1 " "Warning: Ignored 1 CARRY_SUM primitives -- cannot place fan-in logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANIN" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\] " "Warning: Can't place logic feeding CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]\" in single logic cell" { { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~68 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~68\" of type CARRY_SUM" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "CARRY_SUM lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\] " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]\" of type CARRY_SUM" { } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Can't place logic feeding CARRY_SUM primitive \"%1!s!\" in single logic cell" 0 0} } { } 0 0 "Ignored %1!d! CARRY_SUM primitives -- cannot place fan-in logic in single logic cell" 0 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT_HDR" "5 " "Warning: Ignored 5 CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell" { { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\] " "Warning: Can't place logic fed by CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]\" into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~104 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~104\" of type LUT" { } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~108 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~108\" of type LUT" { } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Can't place logic fed by CARRY_SUM primitive \"%1!s!\" into a single logic cell" 0 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~68 " "Warning: Can't place logic fed by CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~68\" into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~108 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~108\" of type LUT" { } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~104 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~104\" of type LUT" { } { { "db/add_sub_n7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Can't place logic fed by CARRY_SUM primitive \"%1!s!\" into a single logic cell" 0 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\] " "Warning: Can't place logic fed by CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]\" into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~69 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~69\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~70 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~70\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Can't place logic fed by CARRY_SUM primitive \"%1!s!\" into a single logic cell" 0 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\] " "Warning: Can't place logic fed by CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]\" into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~53 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~53\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~57 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[3\]~57\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Can't place logic fed by CARRY_SUM primitive \"%1!s!\" into a single logic cell" 0 0} { "Warning" "WFTM_CARRY_MERGE_FANOUT" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\] " "Warning: Can't place logic fed by CARRY_SUM primitive \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]\" into a single logic cell" { { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~61 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~61\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} { "Warning" "WFTM_NODE_NAME" "LUT lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~65 " "Warning: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[2\]~65\" of type LUT" { } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Node \"%2!s!\" of type %1!s!" 0 0} } { { "db/add_sub_m7c.tdf" "" { Text "F:/verilog/實驗三操作/huang/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "Can't place logic fed by CARRY_SUM primitive \"%1!s!\" into a single logic cell" 0 0} } { } 0 0 "Ignored %1!d! CARRY_SUM primitive(s) -- cannot place fan-out logic in single logic cell" 0 0} } { } 0 0 "Ignored %1!d! CARRY_SUM primitives" 0 0}
{ "Info" "IFTM_WANNA_REM_USR_DUPE" "" "Info: Found the following redundant logic cells in design" { { "Info" "IFTM_CELL_NAME" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~100 " "Info: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~100\"" { } { } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "IFTM_CELL_NAME" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~98 " "Info: Node \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~98\"" { } { } 0 0 "Node \"%1!s!\"" 0 0} } { } 0 0 "Found the following redundant logic cells in design" 0 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]~49 " "Info: Logic cell \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]~49\"" { } { } 0 0 "Logic cell \"%1!s!\"" 0 0} { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~98 " "Info: Logic cell \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~98\"" { } { } 0 0 "Logic cell \"%1!s!\"" 0 0} { "Info" "ISCL_SCL_CELL_NAME" "lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~100 " "Info: Logic cell \"lpm_divide:Mod1\|lpm_divide_rnl:auto_generated\|sign_div_unsign_4kh:divider\|alt_u_div_cie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[1\]~100\"" { } { } 0 0 "Logic cell \"%1!s!\"" 0 0} } { } 0 0 "Found the following redundant logic cells in design" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "399 " "Info: Implemented 399 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "373 " "Info: Implemented 373 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 57 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 57 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri May 15 16:13:12 2009 " "Info: Processing ended: Fri May 15 16:13:12 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/verilog/實驗三操作/huang/huang.map.smsg " "Info: Generated suppressed messages file F:/verilog/實驗三操作/huang/huang.map.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0}
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