/**
  ******************************************************************************
  * @file stm8s.h
  * @brief This file contains all HW registers definitions and memory mapping.
  * @author STMicroelectronics - MCD Application Team
  * @version V1.1.0
  * @date 02/27/2009
  ******************************************************************************
  *
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  *
    * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
  * @image html logo.bmp
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM8S_H
#define __STM8S_H

/******************************************************************************/
/*                   Library configuration section                            */
/******************************************************************************/
/* Check the used compiler */
#if defined(__CSMC__)
 #undef _RAISONANCE_
 #define _COSMIC_
#elif defined(__RCST7__)
 #undef _COSMIC_
 #define _RAISONANCE_
#else
 #error "Unsupported Compiler!"          /* Compiler defines not found */
#endif

/* Uncomment the line below according to the target STM8S device used in your
   application. 
   Tip: To avoid modifying this file each time you need to switch between these
        devices, you can define the device in your toolchain compiler preprocessor. */
#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && !defined (STM8S103) && !defined (STM8S903)
 #define STM8S208
 /* #define STM8S207 */
 /* #define STM8S105 */  
 /* #define STM8S103 */
 /* #define STM8S903 */
#endif


#if !defined  USE_STDPERIPH_DRIVER
/* Comment the line below if you will not use the peripherals drivers.
   In this case, these drivers will not be included and the application code will be
   based on direct access to peripherals registers */
  #define USE_STDPERIPH_DRIVER
#endif

/* For FLASH routines, select whether pointer will be declared as near (2 bytes, handle
   code smaller than 64KB) or far (3 bytes, handle code larger than 64K) */
/*#define PointerAttr_Near 1 /*!< Used with memory Models for code smaller than 64K */ 
#define PointerAttr_Far 2 /*!< Used with memory Models for code larger than 64K */ 

#ifdef _COSMIC_
 #define FAR  @far
 #define NEAR @near
#else /* __RCST7__ */
 #define FAR  far
 #define NEAR near
#endif /* __CSMC__ */

#ifdef PointerAttr_Far
 #define PointerAttr FAR 
#else /* PointerAttr_Near */
 #define PointerAttr NEAR
#endif /* PointerAttr_Far */


/* Uncomment the line below to use the cosmic section */
#if defined(_COSMIC_)
/* #define USE_COSMIC_SECTIONS  (1)*/
#endif

/******************************************************************************/

/* Includes ------------------------------------------------------------------*/
#include "stm8s_type.h"

/* Exported types and constants-----------------------------------------------*/
/** @addtogroup MAP_FILE_Exported_Types_and_Constants
  * @{
  */

/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/
/*----------------------------------------------------------------------------*/
/**
  * @brief General Purpose I/Os (GPIO)
  */

typedef struct GPIO_struct
{
  vu8 ODR; /*!< Output Data Register */
  vu8 IDR; /*!< Input Data Register */
  vu8 DDR; /*!< Data Direction Register */
  vu8 CR1; /*!< Configuration Register 1 */
  vu8 CR2; /*!< Configuration Register 2 */
}
GPIO_TypeDef;

/** @addtogroup GPIO_Registers_Reset_Value
  * @{
  */

#define GPIO_ODR_RESET_VALUE ((u8)0x00)
#define GPIO_DDR_RESET_VALUE ((u8)0x00)
#define GPIO_CR1_RESET_VALUE ((u8)0x00)
#define GPIO_CR2_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903)
/**
  * @brief Analog to Digital Converter (ADC1)
  */
typedef struct ADC1_struct
{
  vu8 DB0RH;     /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB0RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB1RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB1RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB2RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB2RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB3RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB3RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB4RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB4RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB5RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB5RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB6RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB6RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB7RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB7RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB8RH;     /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB8RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 DB9RH;      /*!< ADC1 Data Buffer Register (MSB)  */
  vu8 DB9RL;      /*!< ADC1 Data Buffer Register (LSB)  */
  vu8 RESERVED[12]; /*!< Reserved byte */
  vu8 CSR;        /*!< ADC1 control status register */
  vu8 CR1;        /*!< ADC1 configuration register 1 */
  vu8 CR2;        /*!< ADC1 configuration register 2 */
  vu8 CR3;    /*!< ADC1 configuration register 3  */
  vu8 DRH;        /*!< ADC1 Data high */
  vu8 DRL;        /*!< ADC1 Data low */
  vu8 TDRH;       /*!< ADC1 Schmitt trigger disable register high  */
  vu8 TDRL;       /*!< ADC1 Schmitt trigger disable register low */
  vu8 HTRL;   /*!< ADC1 high threshold register Low*/
  vu8 HTRH;   /*!< ADC1 high threshold register High*/
  vu8 LTRH;   /*!< ADC1 low threshold register high */
  vu8 LTRL;   /*!< ADC1 low threshold register low */
  vu8 AWSRH;   /*!< ADC1 watchdog status register high */
  vu8 AWSRL;   /*!< ADC1 watchdog status register low */
  vu8 AWCRH;   /*!< ADC1 watchdog control register high */
  vu8 AWCRL;   /*!< ADC1 watchdog control register low */
}
ADC1_TypeDef;

/** @addtogroup ADC1_Registers_Reset_Value
  * @{
  */

#define  ADC1_CSR_RESET_VALUE  ((u8)0x00)
#define  ADC1_CR1_RESET_VALUE  ((u8)0x00)
#define  ADC1_CR2_RESET_VALUE  ((u8)0x00)
#define  ADC1_CR3_RESET_VALUE  ((u8)0x00)
#define  ADC1_TDRL_RESET_VALUE ((u8)0x00)
#define  ADC1_TDRH_RESET_VALUE ((u8)0x00)
#define  ADC1_HTRL_RESET_VALUE ((u8)0xFF)
#define  ADC1_HTRH_RESET_VALUE ((u8)0x03)
#define  ADC1_LTRH_RESET_VALUE ((u8)0x00)
#define  ADC1_LTRL_RESET_VALUE ((u8)0x00)
#define  ADC1_AWCRH_RESET_VALUE ((u8)0x00)
#define  ADC1_AWCRL_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup ADC1_Registers_Bits_Definition
  * @{
  */

#define ADC1_CSR_EOC  ((u8)0x80) /*!< End of Conversion mask */
#define ADC1_CSR_AWD  ((u8)0x40) /*!< Analog Watch Dog Status mask */
#define ADC1_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */
#define ADC1_CSR_AWDIE ((u8)0x10) /*!< Analog Watchdog interrupt enable mask */
#define ADC1_CSR_CH   ((u8)0x0F) /*!< Channel selection bits mask */

#define ADC1_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */
#define ADC1_CR1_CONT  ((u8)0x02) /*!< Continuous conversion mask */
#define ADC1_CR1_ADON  ((u8)0x01) /*!< A/D Converter on/off mask */

#define ADC1_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */
#define ADC1_CR2_EXTSEL  ((u8)0x30) /*!< External event selection mask */
#define ADC1_CR2_ALIGN   ((u8)0x08) /*!< Data Alignment mask */
#define ADC1_CR2_SCAN   ((u8)0x02) /*!< Scan mode mask */

#define ADC1_CR3_DBUF   ((u8)0x80) /*!< Data Buffer Enable mask */
#define ADC1_CR3_OVR    ((u8)0x40) /*!< Overrun Status Flag mask */

#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Analog to Digital Converter (ADC2)
  */
#if defined(STM8S208) || defined(STM8S207)
typedef struct ADC2_struct
{
  vu8 CSR;        /*!< ADC2 control status register */
  vu8 CR1;        /*!< ADC2 configuration register 1 */
  vu8 CR2;        /*!< ADC2 configuration register 2 */
  vu8 RESERVED;   /*!< Reserved byte */
  vu8 DRH;        /*!< ADC2 Data high */
  vu8 DRL;        /*!< ADC2 Data low */
  vu8 TDRH;       /*!< ADC2 Schmitt trigger disable register high  */
  vu8 TDRL;       /*!< ADC2 Schmitt trigger disable register low */
}
ADC2_TypeDef;

/** @addtogroup ADC2_Registers_Reset_Value
  * @{
  */

#define  ADC2_CSR_RESET_VALUE  ((u8)0x00)
#define  ADC2_CR1_RESET_VALUE  ((u8)0x00)
#define  ADC2_CR2_RESET_VALUE  ((u8)0x00)
#define  ADC2_TDRL_RESET_VALUE ((u8)0x00)
#define  ADC2_TDRH_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup ADC2_Registers_Bits_Definition
  * @{
  */

#define ADC2_CSR_EOC  ((u8)0x80) /*!< End of Conversion mask */
#define ADC2_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */
#define ADC2_CSR_CH   ((u8)0x0F) /*!< Channel selection bits mask */

#define ADC2_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */
#define ADC2_CR1_CONT  ((u8)0x02) /*!< Continuous conversion mask */
#define ADC2_CR1_ADON  ((u8)0x01) /*!< A/D Converter on/off mask */

#define ADC2_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */
#define ADC2_CR2_EXTSEL  ((u8)0x30) /*!< External event selection mask */
#define ADC2_CR2_ALIGN   ((u8)0x08) /*!< Data Alignment mask */

#endif /* (STM8S208) ||(STM8S207)  */
/**
  * @}
  */
/*----------------------------------------------------------------------------*/
/**
  * @brief Auto Wake Up (AWU) peripheral registers.
  */

typedef struct AWU_struct
{
  vu8 CSR; /*!< AWU Control status register */
  vu8 APR; /*!< AWU Asynchronous prescalar buffer */
  vu8 TBR; /*!< AWU Time base selection register */
}
AWU_TypeDef;

/** @addtogroup AWU_Registers_Reset_Value
  * @{
  */

#define AWU_CSR_RESET_VALUE ((u8)0x00)
#define AWU_APR_RESET_VALUE ((u8)0x3F)
#define AWU_TBR_RESET_VALUE ((u8)0x00)

/**
  * @}
  */

/** @addtogroup AWU_Registers_Bits_Definition
  * @{
  */

#define AWU_CSR_AWUF  ((u8)0x20) /*!< Interrupt flag mask */
#define AWU_CSR_AWUEN ((u8)0x10) /*!< Auto Wake-up enable mask */
#define AWU_CSR_MR    ((u8)0x02) /*!< Master Reset mask */
#define AWU_CSR_MSR   ((u8)0x01) /*!< Measurement enable mask */

#define AWU_APR_APR ((u8)0x3F) /*!< Asynchronous Prescaler divider mask */

#define AWU_TBR_AWUTB ((u8)0x0F) /*!< Timebase selection mask */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Beeper (BEEP) peripheral registers.
  */

typedef struct BEEP_struct
{
  vu8 CSR; /*!< BEEP Control status register */
}
BEEP_TypeDef;

/** @addtogroup BEEP_Registers_Reset_Value
  * @{
  */

#define BEEP_CSR_RESET_VALUE ((u8)0x1F)

/**