?? stm8s.h
字號(hào):
* @brief External Interrupt Controller (EXTI)
*/
typedef struct EXTI_struct
{
vu8 CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
vu8 CR2; /*!< External Interrupt Control Register for PORTE and TLI */
}
EXTI_TypeDef;
/** @addtogroup EXTI_Registers_Reset_Value
* @{
*/
#define EXTI_CR1_RESET_VALUE ((u8)0x00)
#define EXTI_CR2_RESET_VALUE ((u8)0x00)
/**
* @}
*/
/** @addtogroup EXTI_Registers_Bits_Definition
* @{
*/
#define EXTI_CR1_PDIS ((u8)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
#define EXTI_CR1_PCIS ((u8)0x30) /*!< PORTC external interrupt sensitivity bits mask */
#define EXTI_CR1_PBIS ((u8)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
#define EXTI_CR1_PAIS ((u8)0x03) /*!< PORTA external interrupt sensitivity bits mask */
#define EXTI_CR2_TLIS ((u8)0x04) /*!< Top level interrupt sensitivity bit mask */
#define EXTI_CR2_PEIS ((u8)0x03) /*!< PORTE external interrupt sensitivity bits mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief FLASH program and Data memory (FLASH)
*/
typedef struct FLASH_struct
{
vu8 CR1; /*!< Flash control register 1 */
vu8 CR2; /*!< Flash control register 2 */
vu8 NCR2; /*!< Flash complementary control register 2 */
vu8 FPR; /*!< Flash protection register */
vu8 NFPR; /*!< Flash complementary protection register */
vu8 IAPSR; /*!< Flash in-application programming status register */
vu8 RESERVED1; /*!< Reserved byte */
vu8 RESERVED2; /*!< Reserved byte */
vu8 PUKR; /*!< Flash program memory unprotection register */
vu8 RESERVED3; /*!< Reserved byte */
vu8 DUKR; /*!< Data EEPROM unprotection register */
}
FLASH_TypeDef;
/** @addtogroup FLASH_Registers_Reset_Value
* @{
*/
#define FLASH_CR1_RESET_VALUE ((u8)0x00)
#define FLASH_CR2_RESET_VALUE ((u8)0x00)
#define FLASH_NCR2_RESET_VALUE ((u8)0xFF)
#define FLASH_IAPSR_RESET_VALUE ((u8)0x40)
#define FLASH_PUKR_RESET_VALUE ((u8)0x00)
#define FLASH_DUKR_RESET_VALUE ((u8)0x00)
/**
* @}
*/
/** @addtogroup FLASH_Registers_Bits_Definition
* @{
*/
#define FLASH_CR1_HALT ((u8)0x08) /*!< Standby in Halt mode mask */
#define FLASH_CR1_AHALT ((u8)0x04) /*!< Standby in Active Halt mode mask */
#define FLASH_CR1_IE ((u8)0x02) /*!< Flash Interrupt enable mask */
#define FLASH_CR1_FIX ((u8)0x01) /*!< Fix programming time mask */
#define FLASH_CR2_OPT ((u8)0x80) /*!< Select option byte mask */
#define FLASH_CR2_WPRG ((u8)0x40) /*!< Word Programming mask */
#define FLASH_CR2_ERASE ((u8)0x20) /*!< Erase block mask */
#define FLASH_CR2_FPRG ((u8)0x10) /*!< Fast programming mode mask */
#define FLASH_CR2_PRG ((u8)0x01) /*!< Program block mask */
#define FLASH_NCR2_NOPT ((u8)0x80) /*!< Select option byte mask */
#define FLASH_NCR2_NWPRG ((u8)0x40) /*!< Word Programming mask */
#define FLASH_NCR2_NERASE ((u8)0x20) /*!< Erase block mask */
#define FLASH_NCR2_NFPRG ((u8)0x10) /*!< Fast programming mode mask */
#define FLASH_NCR2_NPRG ((u8)0x01) /*!< Program block mask */
#define FLASH_IAPSR_HVOFF ((u8)0x40) /*!< End of high voltage flag mask */
#define FLASH_IAPSR_DUL ((u8)0x08) /*!< Data EEPROM unlocked flag mask */
#define FLASH_IAPSR_EOP ((u8)0x04) /*!< End of operation flag mask */
#define FLASH_IAPSR_PUL ((u8)0x02) /*!< Flash Program memory unlocked flag mask */
#define FLASH_IAPSR_WR_PG_DIS ((u8)0x01) /*!< Write attempted to protected page mask */
#define FLASH_PUKR_PUK ((u8)0xFF) /*!< Flash Program memory unprotection mask */
#define FLASH_DUKR_DUK ((u8)0xFF) /*!< Data EEPROM unprotection mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Option Bytes (OPT)
*/
typedef struct OPT_struct
{
vu8 OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
vu8 OPT1; /*!< Option byte 1: User boot code */
vu8 NOPT1; /*!< Complementary Option byte 1 */
vu8 OPT2; /*!< Option byte 2: Alternate function remapping */
vu8 NOPT2; /*!< Complementary Option byte 2 */
vu8 OPT3; /*!< Option byte 3: Watchdog option */
vu8 NOPT3; /*!< Complementary Option byte 3 */
vu8 OPT4; /*!< Option byte 4: Clock option */
vu8 NOPT4; /*!< Complementary Option byte 4 */
vu8 OPT5; /*!< Option byte 5: HSE clock startup */
vu8 NOPT5; /*!< Complementary Option byte 5 */
vu8 RESERVED1; /*!< Reserved Option byte*/
vu8 RESERVED2; /*!< Reserved Option byte*/
vu8 OPT7; /*!< Option byte 7: flash wait states */
vu8 NOPT7; /*!< Complementary Option byte 7 */
}
OPT_TypeDef;
/*----------------------------------------------------------------------------*/
/**
* @brief Independent Watchdog (IWDG)
*/
typedef struct IWDG_struct
{
vu8 KR; /*!< Key Register */
vu8 PR; /*!< Prescaler Register */
vu8 RLR; /*!< Reload Register */
}
IWDG_TypeDef;
/** @addtogroup IWDG_Registers_Reset_Value
* @{
*/
#define IWDG_PR_RESET_VALUE ((u8)0x00)
#define IWDG_RLR_RESET_VALUE ((u8)0xFF)
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Window Watchdog (WWDG)
*/
typedef struct WWDG_struct
{
vu8 CR; /*!< Control Register */
vu8 WR; /*!< Window Register */
}
WWDG_TypeDef;
/** @addtogroup WWDG_Registers_Reset_Value
* @{
*/
#define WWDG_CR_RESET_VALUE ((u8)0x7F)
#define WWDG_WR_RESET_VALUE ((u8)0x7F)
/**
* @}
*/
/** @addtogroup WWDG_Registers_Bits_Definition
* @{
*/
#define WWDG_CR_WDGA ((u8)0x80) /*!< WDGA bit mask */
#define WWDG_CR_T6 ((u8)0x40) /*!< T6 bit mask */
#define WWDG_CR_T ((u8)0x7F) /*!< T bits mask */
#define WWDG_WR_MSB ((u8)0x80) /*!< MSB bit mask */
#define WWDG_WR_W ((u8)0x7F) /*!< W bits mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Reset Controller (RST)
*/
typedef struct RST_struct
{
vu8 SR; /*!< Reset status register */
}
RST_TypeDef;
/** @addtogroup RST_Registers_Bits_Definition
* @{
*/
#define RST_SR_EMCF ((u8)0x10) /*!< EMC reset flag bit mask */
#define RST_SR_SWIMF ((u8)0x08) /*!< SWIM reset flag bit mask */
#define RST_SR_ILLOPF ((u8)0x04) /*!< Illegal opcode reset flag bit mask */
#define RST_SR_IWDGF ((u8)0x02) /*!< IWDG reset flag bit mask */
#define RST_SR_WWDGF ((u8)0x01) /*!< WWDG reset flag bit mask */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Serial Peripheral Interface (SPI)
*/
typedef struct SPI_struct
{
vu8 CR1; /*!< SPI control register 1 */
vu8 CR2; /*!< SPI control register 2 */
vu8 ICR; /*!< SPI interrupt control register */
vu8 SR; /*!< SPI status register */
vu8 DR; /*!< SPI data I/O register */
vu8 CRCPR; /*!< SPI CRC polynomial register */
vu8 RXCRCR; /*!< SPI Rx CRC register */
vu8 TXCRCR; /*!< SPI Tx CRC register */
}
SPI_TypeDef;
/** @addtogroup SPI_Registers_Reset_Value
* @{
*/
#define SPI_CR1_RESET_VALUE ((u8)0x00) /*!< Control Register 1 reset value */
#define SPI_CR2_RESET_VALUE ((u8)0x00) /*!< Control Register 2 reset value */
#define SPI_ICR_RESET_VALUE ((u8)0x00) /*!< Interrupt Control Register reset value */
#define SPI_SR_RESET_VALUE ((u8)0x02) /*!< Status Register reset value */
#define SPI_DR_RESET_VALUE ((u8)0x00) /*!< Data Register reset value */
#define SPI_CRCPR_RESET_VALUE ((u8)0x07) /*!< Polynomial Register reset value */
#define SPI_RXCRCR_RESET_VALUE ((u8)0x00) /*!< RX CRC Register reset value */
#define SPI_TXCRCR_RESET_VALUE ((u8)0x00) /*!< TX CRC Register reset value */
/**
* @}
*/
/** @addtogroup SPI_Registers_Bits_Definition
* @{
*/
#define SPI_CR1_LSBFIRST ((u8)0x80) /*!< Frame format mask */
#define SPI_CR1_SPE ((u8)0x40) /*!< Enable bits mask */
#define SPI_CR1_BR ((u8)0x38) /*!< Baud rate control mask */
#define SPI_CR1_MSTR ((u8)0x04) /*!< Master Selection mask */
#define SPI_CR1_CPOL ((u8)0x02) /*!< Clock Polarity mask */
#define SPI_CR1_CPHA ((u8)0x01) /*!< Clock Phase mask */
#define SPI_CR2_BDM ((u8)0x80) /*!< Bi-directional data mode enable mask */
#define SPI_CR2_BDOE ((u8)0x40) /*!< Output enable in bi-directional mode mask */
#define SPI_CR2_CRCEN ((u8)0x20) /*!< Hardware CRC calculation enable mask */
#define SPI_CR2_CRCNEXT ((u8)0x10) /*!< Transmit CRC next mask */
#define SPI_CR2_RXONLY ((u8)0x04) /*!< Receive only mask */
#define SPI_CR2_SSM ((u8)0x02) /*!< Software slave management mask */
#define SPI_CR2_SSI ((u8)0x01) /*!< Internal slave select mask */
#define SPI_ICR_TXEI ((u8)0x80) /*!< Tx buffer empty interrupt enable mask */
#define SPI_ICR_RXEI ((u8)0x40) /*!< Rx buffer empty interrupt enable mask */
#define SPI_ICR_ERRIE ((u8)0x20) /*!< Error interrupt enable mask */
#define SPI_ICR_WKIE ((u8)0x10) /*!< Wake-up interrupt enable mask */
#define SPI_SR_BSY ((u8)0x80) /*!< Busy flag */
#define SPI_SR_OVR ((u8)0x40) /*!< Overrun flag */
#define SPI_SR_MODF ((u8)0x20) /*!< Mode fault */
#define SPI_SR_CRCERR ((u8)0x10) /*!< CRC error flag */
#define SPI_SR_WKUP ((u8)0x08) /*!< Wake-Up flag */
#define SPI_SR_TXE ((u8)0x02) /*!< Transmit buffer empty */
#define SPI_SR_RXNE ((u8)0x01) /*!< Receive buffer not empty */
/**
* @}
*/
/*----------------------------------------------------------------------------*/
/**
* @brief Single Wire Interface Module (SWIM)
*/
typedef struct SWIM_struct
{
vu8 CSR; /*!< Control/Status register */
vu8 DR; /*!< Data register */
}
SWIM_TypeDef;
/*----------------------------------------------------------------------------*/
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)
*/
typedef struct UART1_struct
{
vu8 SR; /*!< UART1 status register */
vu8 DR; /*!< UART1 data register */
vu8 BRR1; /*!< UART1 baud rate register */
vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
vu8 CR1; /*!< UART1 control register 1 */
vu8 CR2; /*!< UART1 control register 2 */
vu8 CR3; /*!< UART1 control register 3 */
vu8 CR4; /*!< UART1 control register 4 */
vu8 CR5; /*!< UART1 control register 5 */
vu8 GTR; /*!< UART1 guard time register */
vu8 PSCR; /*!< UART1 prescaler register */
}
UART1_TypeDef;
/** @addtogroup UART1_Registers_Reset_Value
* @{
*/
#define UART1_SR_RESET_V?? 快捷鍵說明
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