/********************************************************************************/
/* Project: EDMA Test                                                           */
/* mcbsp.c                                                                      */
/* written by David Bell                                                        */
/*         on 6/21/99                                                           */
/*                                                                              */
/* mcbsp.c configures the McBSPs as required for the EDMA transfers on channels */
/* 12 - 15. The McBSP in use is configured to operate in digital loopback (DLB) */
/* mode, such that the data transferred is looped back to the receive port in-  */
/* ternally.                                                                    */
/*                                                                              */
/********************************************************************************/

#include <csl.h>
#include <csl_mcbsp.h>


/* prototypes */
void cfg_mcbsp(MCBSP_Handle *hMcbsp_ch0);
void start_mcbsp(MCBSP_Handle *hMcbsp_ch0);

/***********************************cfg_mcbsp************************************/
/* Program McBSP0 to transmit and receive 32-bit elements in digital loopback.  */
/********************************************************************************/
void
cfg_mcbsp(MCBSP_Handle *hMcbsp_ch0)
{
MCBSP_Config config;

      *hMcbsp_ch0 = MCBSP_open(0, MCBSP_OPEN_RESET);
      
      /* Set up Serial Port Control Register */
      config.spcr = (Uint32)
                   ((MCBSP_SPCR_XINTM_XRDY     << _MCBSP_SPCR_XINTM_SHIFT)
                  | (MCBSP_SPCR_RINTM_RRDY     << _MCBSP_SPCR_RINTM_SHIFT)
                  | (MCBSP_SPCR_DLB_ON         << _MCBSP_SPCR_DLB_SHIFT  ));

      /* Set up Pin Control Register */
      config.pcr  = (Uint32)
                   ((MCBSP_PCR_FSXM_INTERNAL   << _MCBSP_PCR_FSXM_SHIFT)
                  | (MCBSP_PCR_FSRM_INTERNAL   << _MCBSP_PCR_FSXM_SHIFT)
                  | (MCBSP_PCR_CLKXM_OUTPUT    << _MCBSP_PCR_CLKXM_SHIFT)
                  | (MCBSP_PCR_CLKRM_OUTPUT    << _MCBSP_PCR_CLKRM_SHIFT)
                  | (MCBSP_PCR_FSXP_ACTIVEHIGH << _MCBSP_PCR_FSXP_SHIFT)
                  | (MCBSP_PCR_FSRP_ACTIVEHIGH << _MCBSP_PCR_FSRP_SHIFT)
                  | (MCBSP_PCR_CLKXP_RISING    << _MCBSP_PCR_CLKXP_SHIFT)
                  | (MCBSP_PCR_CLKRP_FALLING   << _MCBSP_PCR_CLKRP_SHIFT));
                  
      /* Set up Receive Control Register */
      config.rcr  = (Uint32)
                   ((MCBSP_RCR_RPHASE_SINGLE   << _MCBSP_RCR_RPHASE_SHIFT  )
                  | (MCBSP_RCR_RFIG_YES        << _MCBSP_RCR_RFIG_SHIFT    )
                  | (MCBSP_RCR_RDATDLY_1BIT    << _MCBSP_RCR_RDATDLY_SHIFT )
                  | (MCBSP_RCR_RFRLEN1_OF(0)   << _MCBSP_RCR_RFRLEN1_SHIFT )
                  | (MCBSP_RCR_RWDLEN1_32BIT   << _MCBSP_RCR_RWDLEN1_SHIFT )
                  | (MCBSP_RCR_RCOMPAND_MSB    << _MCBSP_RCR_RCOMPAND_SHIFT));

      /* Set up Transmit Control Register */
      config.xcr  = (Uint32)
                   ((MCBSP_XCR_XPHASE_SINGLE   << _MCBSP_XCR_XPHASE_SHIFT  )
                  | (MCBSP_XCR_XFIG_YES        << _MCBSP_XCR_XFIG_SHIFT    )
                  | (MCBSP_XCR_XDATDLY_1BIT    << _MCBSP_XCR_XDATDLY_SHIFT )
                  | (MCBSP_XCR_XFRLEN1_OF(0)   << _MCBSP_XCR_XFRLEN1_SHIFT )
                  | (MCBSP_XCR_XWDLEN1_32BIT   << _MCBSP_XCR_XWDLEN1_SHIFT )
                  | (MCBSP_XCR_XCOMPAND_MSB    << _MCBSP_XCR_XCOMPAND_SHIFT));

      /* Set up Sample Rate Generator Register */
      config.srgr = (Uint32)
                   ((MCBSP_SRGR_CLKSM_INTERNAL << _MCBSP_SRGR_CLKSM_SHIFT )
                  | (MCBSP_SRGR_FSGM_DXR2XSR   << _MCBSP_SRGR_FSGM_SHIFT  )
                  | (MCBSP_SRGR_CLKGDV_OF(7)   << _MCBSP_SRGR_CLKGDV_SHIFT));

      MCBSP_config(*hMcbsp_ch0, &config);
      
} /* end config_mcbsp */


void
start_mcbsp(MCBSP_Handle *hMcbsp_ch0)
{
      /* Bring McBSPs out of reset */
      MCBSP_enableSrgr(*hMcbsp_ch0);             /* Start Sample Rate Generator */
      MCBSP_enableFsync(*hMcbsp_ch0);            /* Enable Frame Sync pulse     */
      MCBSP_enableRcv(*hMcbsp_ch0);              /* Bring Receive out of reset  */
      MCBSP_enableXmt(*hMcbsp_ch0);              /* Bring Transmit out of reset */

} /* end start_mcbsp */