module	LCD_TEST (	//	Host Side					iCLK,iRST_N,					//	LCD Side					LCD_DATA,LCD_RW,LCD_EN,LCD_RS	);//	Host Sideinput			iCLK;//	輸入時鐘為50Minput 	  iRST_N;////	LCD Sideoutput	[7:0]	LCD_DATA;output			LCD_RW,LCD_EN,LCD_RS;//	Internal Wires/Registersreg	[5:0]	LUT_INDEX;reg	[8:0]	LUT_DATA;reg	[5:0]	mLCD_ST;			//LCD state registerreg	[17:0]	mDLY;				//delay registerreg			mLCD_Start;reg	[7:0]	mLCD_DATA;reg			mLCD_RS;wire		mLCD_Done;parameter	LCD_INTIAL	=	0;parameter	LCD_LINE1	=	5;							//前5個LUT的數據用于初始化，																			//故第一行的數據從LUT_INDEX=5開始parameter	LCD_CH_LINE	=	LCD_LINE1+16;	//換行索引parameter	LCD_LINE2	=	LCD_LINE1+16+1;	//第二行的起始索引parameter	LUT_SIZE	=	LCD_LINE1+32+1;//查找表的大小always@(posedge iCLK or negedge iRST_N)begin	if(!iRST_N)				//reset	begin		LUT_INDEX	<=	0;		mLCD_ST		<=	0;		mDLY		<=	0;		mLCD_Start	<=	0;		mLCD_DATA	<=	0;		mLCD_RS		<=	0;	end	else	begin		if(LUT_INDEX<LUT_SIZE)		//LUT_SIZE	=	LCD_LINE1+32+1;	LCD_LINE1	=	5;		begin			case(mLCD_ST)			0:	begin					mLCD_DATA	<=	LUT_DATA[7:0];					mLCD_RS		<=	LUT_DATA[8];					mLCD_Start	<=	1;					mLCD_ST		<=	1;				end			1:	begin					if(mLCD_Done)					begin						mLCD_Start	<=	0;						mLCD_ST		<=	2;										end				end			2:	begin					if(mDLY<18'h3FFFE)		//顯示延時5.24ms					//if(mDLY<18'h3)							mDLY	<=	mDLY+1;					else					begin						mDLY	<=	0;						mLCD_ST	<=	3;					end				end			3:	begin					LUT_INDEX	<=	LUT_INDEX+1;	//訪問下一個查找表（的數據）					mLCD_ST	<=	0;				end			endcase		end	endendalways @(LUT_INDEX)//@(posedge iCLK )begin	case(LUT_INDEX)	//	Initial	LCD_INTIAL+0:	LUT_DATA	<=	9'h038;		//Function Set：																				/*9'h038=9'b0_0011_1000:																					位4：1，顯示數據長度為：8 bit;																					位3：1，顯示2行																					位2：0，顯示點陣為5*8																					位1、位0：無關位*/	LCD_INTIAL+1:	LUT_DATA	<=	9'h00C;		//Display ON/OFF Control																				/*9'h00C=9'b0_0000_1100:																					位2：1，打開顯示																					位1：1，顯示光標																					位0：0，光標不閃爍*/	LCD_INTIAL+2:	LUT_DATA	<=	9'h001;		//Clear Display	LCD_INTIAL+3:	LUT_DATA	<=	9'h006;		//Entry Mode Set																				/*9'h006=9'b0_0000_0110:																					TOTEST*/	LCD_INTIAL+4:	LUT_DATA	<=	9'h080;		//Set DDRAM Address																				/*設置DDRAM 的地址：AC（address counter）=0*/	//	Line 1   //	Welcome to the	LCD_LINE1+0:	LUT_DATA	<=	9'h120;	   //" " blank	LCD_LINE1+1:	LUT_DATA	<=	9'h157;   //W	LCD_LINE1+2:	LUT_DATA	<=	9'h165;   //e	LCD_LINE1+3:	LUT_DATA	<=	9'h16C;   //l	LCD_LINE1+4:	LUT_DATA	<=	9'h163;   //c	LCD_LINE1+5:	LUT_DATA	<=	9'h16F;   //o	LCD_LINE1+6:	LUT_DATA	<=	9'h16D;   //m	LCD_LINE1+7:	LUT_DATA	<=	9'h165;   //e	LCD_LINE1+8:	LUT_DATA	<=	9'h120;   //" "	LCD_LINE1+9:	LUT_DATA	<=	9'h174;   //t	LCD_LINE1+10:	LUT_DATA	<=	9'h16F;   //o	LCD_LINE1+11:	LUT_DATA	<=	9'h120;   //" "	LCD_LINE1+12:	LUT_DATA	<=	9'h174;   //t	LCD_LINE1+13:	LUT_DATA	<=	9'h168;   //h	LCD_LINE1+14:	LUT_DATA	<=	9'h165;   //e	LCD_LINE1+15:	LUT_DATA	<=	9'h120;   //" "	//	Change Line	LCD_CH_LINE:	LUT_DATA	<=	9'h0C0;   //change line instruction	//	Line 2	LCD_LINE2+0:	LUT_DATA	<=	9'h141;	//	Altera DE2 Board	LCD_LINE2+1:	LUT_DATA	<=	9'h16C;	LCD_LINE2+2:	LUT_DATA	<=	9'h174;	LCD_LINE2+3:	LUT_DATA	<=	9'h165;	LCD_LINE2+4:	LUT_DATA	<=	9'h172;	LCD_LINE2+5:	LUT_DATA	<=	9'h161;	LCD_LINE2+6:	LUT_DATA	<=	9'h120;	LCD_LINE2+7:	LUT_DATA	<=	9'h144;	LCD_LINE2+8:	LUT_DATA	<=	9'h145;	LCD_LINE2+9:	LUT_DATA	<=	9'h132;	LCD_LINE2+10:	LUT_DATA	<=	9'h120;	LCD_LINE2+11:	LUT_DATA	<=	9'h142;	LCD_LINE2+12:	LUT_DATA	<=	9'h16F;	LCD_LINE2+13:	LUT_DATA	<=	9'h161;	LCD_LINE2+14:	LUT_DATA	<=	9'h172;	LCD_LINE2+15:	LUT_DATA	<=	9'h164;	default:		LUT_DATA	<=	9'h000;	endcaseendLCD_Controller 		u0	(	//	Host Side							.iDATA(mLCD_DATA),							.iRS(mLCD_RS),							.iStart(mLCD_Start),							.oDone(mLCD_Done),							.iCLK(iCLK),							.iRST_N(iRST_N),							//	LCD Interface							.LCD_DATA(LCD_DATA),							.LCD_RW(LCD_RW),							.LCD_EN(LCD_EN),							.LCD_RS(LCD_RS)	);endmodule