addra_reg = addra_in;	    wea_reg = wea_in;	    dia_reg = dia_in;	    dipa_reg = dipa_in;	end    end    always @(posedge clkb_in) begin	rising_clkb = 1;		if (enb_in === 1'b1) begin	    prev_time = curr_time;	    curr_time = $time;	    addrb_reg = addrb_in;	    web_reg = web_in;	    enb_reg = enb_in;	    dib_reg = dib_in;	    dipb_reg = dipb_in;	end    end // always @ (posedge clkb_in)        always @(posedge rising_clka or posedge rising_clkb) begin	if (rising_clka)	    if (cascade_a[1])		addra_in_15_reg_bram = ~addra_in[15];	    else		addra_in_15_reg_bram = addra_in[15];	if (rising_clkb)	    if (cascade_b[1])		addrb_in_15_reg_bram = ~addrb_in[15];	    else		addrb_in_15_reg_bram = addrb_in[15];		if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00)))  begin/************************************* Collision starts *****************************************/	  if (SIM_COLLISION_CHECK != "NONE") begin	    	    if (gsr_in === 1'b0) begin		if (curr_time - prev_time == 0) begin		    viol_time = 1;		end		else if (curr_time - prev_time <= SETUP_READ_FIRST) begin		    viol_time = 2;		end				if (ena_in === 1'b0 || enb_in === 1'b0)		    viol_time = 0;				if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))		    if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))			viol_time = 0;		 				if (viol_time != 0) begin		    		    if (rising_clka && rising_clkb) begin			if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin			    			    viol_type = 2'b01;			    task_rd_ram_a (addra_in, doa_buf, dopa_buf);			    task_rd_ram_b (addrb_in, dob_buf, dopb_buf);			    task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in);			    task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in);			    task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf);			    task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf);			    task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in);			    			    if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_in === 1'b1) begin				dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);								eccparity_out = dip_ecc_col;				task_col_wr_ram_b (2'b10, wea_in, web_in, dib_in, dip_ecc_col, addra_in, addrb_in);			    end			    else				task_col_wr_ram_b (2'b10, wea_in, web_in, dib_in, dipb_in, addra_in, addrb_in);			    			    if (wr_mode_a != 2'b01)				task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf);			    if (wr_mode_b != 2'b01)				task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf);			    if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")				task_col_ecc_read (doa_buf, dopa_buf, addra_in);							    			end // if (addra_in[14:col_addr_lsb] === addrb_in[14:col_addr_lsb])			else			    viol_time = 0;					    end		    else if (rising_clka && !rising_clkb) begin			if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) begin			    			    viol_type = 2'b10;			    task_rd_ram_a (addra_in, doa_buf, dopa_buf);			    			    task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in);			    task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg);			    			    task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf);			    task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);			    			    task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in);			    			    if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_reg === 1'b1) begin				dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg);								eccparity_out = dip_ecc_col;				task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_reg, dip_ecc_col, addra_in, addrb_reg);			    end			    else				task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_reg, dipb_reg, addra_in, addrb_reg);			    			    if (wr_mode_a != 2'b01)				task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf);			    if (wr_mode_b != 2'b01)				task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf);			    if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")				task_col_ecc_read (doa_buf, dopa_buf, addra_in);			    			end // if (addra_in[14:col_addr_lsb] === addrb_reg[14:col_addr_lsb])			else			    viol_time = 0;					    end		    else if (!rising_clka && rising_clkb) begin			if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) begin			    			    viol_type = 2'b11;			    task_rd_ram_b (addrb_in, dob_buf, dopb_buf);			    task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg);			    task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in);			    			    task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);			    task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);			    task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg);			    if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_in === 1'b1) begin				dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in);								eccparity_out = dip_ecc_col;				task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_in, dip_ecc_col, addra_reg, addrb_in);			    end			    else				task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_in, dipb_in, addra_reg, addrb_in);			    			    if (wr_mode_a != 2'b01)			    				task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf);			    if (wr_mode_b != 2'b01)				task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf);			    			    if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")				task_col_ecc_read (doa_buf, dopa_buf, addra_reg);			    			end // if (addra_reg[14:col_addr_lsb] === addrb_in[14:col_addr_lsb])			else			    viol_time = 0;					    end		    		end // if (viol_time != 0)	    end // if (gsr_in === 1'b0)	      	    if (SIM_COLLISION_CHECK == "WARNING_ONLY")		viol_time = 0;	    	  end // if (SIM_COLLISION_CHECK != "NONE")	/*************************************** end collision ********************************/	end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00)))		/**************************** Port A ****************************************/	if (rising_clka) begin	    // DRC	    if (ssra_in === 1 && BRAM_MODE == "ECC")		$display("DRC Warning : SET/RESET (SSR) is not supported in ECC mode on ARAMB36_INTERNAL instance %m.");	    if (ssra_in === 1 && BRAM_SIZE == 16 && DOA_REG == 1) begin		$display("DRC Error : SET/RESET (SSR) is not supported when optional output registers are used on ARAMB36_INTERNAL instance %m.");		$finish;	    end	    	    	    	    // registering addra_in[15] the second time	    if (regcea_in)		addra_in_15_reg1 = addra_in_15_reg;   	    		    if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || ssra_in == 1'b1))		if (cascade_a[1])		    addra_in_15_reg = ~addra_in[15];		else		    addra_in_15_reg = addra_in[15];			    if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin				if (ssra_in == 1'b1 && DOA_REG == 0) begin		    doa_buf = SRVAL_A[0 +: ra_width];		    doa_out = SRVAL_A[0 +: ra_width];		    		    if (ra_width >= 8) begin			dopa_buf = SRVAL_A[ra_width +: ra_widthp];			dopa_out = SRVAL_A[ra_width +: ra_widthp];		    end		end				if (viol_time == 0) begin		    if ((wr_mode_a == 2'b01 && (ssra_in === 1'b0 ||