/*****************************************************************************************************
		Example code showing the DMA transfer from linkport 0 to external memory and then a transfer
		from external memory back out to link port 0.

******************************************************************************************************/
#define N 64				// Number of words to be transfered

.extern link_data_rx2;


.section reset;
/************************* Disable all link ports, DMA's and Vector Interrupts************************/

	XR0 = 0x00000000;;		
	XR1 = 0x00000000;;
	XR2 = 0x00000000;;
	XR3 = 0x00000000;;
	LCTL0 = XR0	;;			// Link disable & clear
	LCTL1 = XR0	;;			// Link disable & clear
	LCTL2 = XR0	;;			// Link disable & clear
	LCTL3 = XR0	;;			// Link disable & clear
	XR1 = 0x00040004;;		// count =4, modify = 4
	XR3 = 0x00000000;;		// disable DMA
	DC4 = XR3:0;;			// disable link 0 tx DMA
	DC5 = XR3:0;;			// disable link 1 tx DMA
	DC6 = XR3:0;;			// disable link 2 tx DMA
	DC7 = XR3:0;;			// disable link 3 tx DMA
	DC8 = XR3:0;;			// disable link 0 rx DMA
	DC9 = XR3:0;;			// disable link 1 rx DMA
	DC10 = XR3:0;;			// disable link 2 rx DMA
	DC11 = XR3:0;;			// disable link 3 rx DMA

	xr0 = 0x90010000;;
	xr1 = 0x00000000;;
	IMASKH = xr0;;			// enable emulation debug, Global enable HW interrupts and enable vector interrupts
	IMASKL = xr1;;			// disable all interrupt vector DMA channels until required
/************************************************************************/

/************************* System Control and SDRAM setup ************************/
	/* Setting Up of Control Registers */

	j14 = j31 + 0x3879e7;;				
	SYSCON = j14;;						// 0000000000 1 1 1 0 0 00 11 1 1 00 11 1 1 00 11 1
										// |RESERVED| | | | | |  |  | | |  |  | | |  |  | |
										//			  | | | | |  |  | | |  |  | | |  |  | Bank 0 idle
										//			  | | | | |  |  | | |  |  | | |  |  Bank 0 Internal wait
										//			  | | | | |  |  | | |  |  | | |  Bank 0 Pipe depth
										//			  | | | | |  |  | | |  |  | | Bank 0 Slow
  									    //			  | | | | |  |  | | |  |  | Bank 1 idle
   										//			  | | | | |  |  | | |  |  Bank 1 Internal wait
										//			  | | | | |  |  | | |  Bank 1 Pipe depth
										//			  | | | | |  |  | | Bank 1 Slow
										//			  | | | | |  |  | Host idle
										//			  | | | | |  |  Host Internal wait
										//			  | | | | |  Host Pipe depth  
										//			  | | | | Host Slow 
										//			  | | | Not used
  									    //			  | | Bus width Memory
 									    //			  | Bus width Multiprocessor
										//            Bus width Host
   	

	j11 = j31 + 0x00005B05;;					
	SDRCON = j11;;  					// 00000000000000000 1 011 01 10 0 00 0 10 1
										// |---RESERVED----| |  |   |  | |  | |  | |
										//					 |  |   |  | |  | |  | SDRAM Enabled
										//					 |  |   |  | |  | |  CAS Latency = 3 cycles
										//					 |  |   |  | |  | Pipe Depth = 0 cycles
										//					 |  |   |  | |  Page Boundary = 256 Words
										//					 |  |   |  | Reserved
										//					 |  |   |  Refresh Rate = every 1200 cycles
										//					 |  |   Precharge to RAS Delay = three cycles
										//					 |  RAS to Precharge Delay = 5 cycles
										//					 Init Sequence refresh then MRS
/************************************************************************/


	xr0 = IMASKL;;						 
	xr1 = 0x20400000;;
	xr0 = r0 or r1;;
	IMASKL = xr0;;						// enable DMA5 & DMA9 interrupt---link 1 tx & rx DMA

	j0 = j31 + _dma_int;;				// set DMA interrupt vector
	IVDMA4 = j0;;		
	IVDMA8 = j0;;
	


	XR0 = 0x000004DA;;					//00000000000000000000 0 1 0 0 1 1 011 0 1 0
										//|-----RESERVED-----| | | | | | |  |  | | |
										//					   | | | | | |  |  | | RESERVED
										//					   | | | | | |  |  | Direction Enable (enabled)
										//					   | | | | | |  |  Verification Enable (disabled)
										//					   | | | | | |  SPD Transfer speed 000=CCLK/8, 001=CCLK/4, 010=CCLK/3, 011=CCLK/2
										//					   | | | | | Transmit Enable (enabled)
										//					   | | | | Packet Size 0=64 quads in one packet, 1=Indefinite number of bytes in one packet
										//					   | | | Transmit Time Out Check Enable (disabled)
										//					   | | Connectivity Error Check Enable (disabled)
										//					   | Receive Enable (enabled)
										//					   Receive Time Out Check Enable
	
	xr8 = N;;							// Count value
	xr9 = lshift r8 by 16;;				// Shift count value so ready to be ORed with modify value
	xr10 = 4;;							// Modify value	
	xr4 = link_data_rx2;;				// Destination index
	xr5 = r9 or r10;;					// 0000000001000000 0000000000000100
										// |--------------| |--------------|
										//		  |                 |
										//	      |					Modify Value
										//		  Number of normal words to be transferred
									
	xr6 = 0x00000000;;					// Not a 2 dimensional array so value does not matter
	xr7 = 0x87000000;;					// 100 0 0 11 1 0 0 00000 00 000000000000000
										//  |  | |  | | | |   |    |        |
										//  |  | |  | | | |   |    |        Chain Pointer Quad Word Address
										//  |  | |  | | | |   |    Memory select for chain pointer
										//  |  | |  | | | |   Chaining Destination Channel
										//  |  | |  | | | Chaining Enabled (disabled)
										//  |  | |  | | DMA Request Enable (0=once DMA channel is enabled entire block is transferred)
										//  |  | |  | Interrupt Enable (enabled)
										//  |  | |  Operand Length 00=Reserved, 01=Normal word, 10=Long word, 11=Quad word
										//  |  | Two Dimensional DMA (disabled)
										//  |  Determines Priority 0=DMA request priority normal 1=high
										//  Specify Device Type (010=Internal memory)

	LCTL0 = XR0;;					// Link port 1 control setup
	DC8 = xr7:4;;						// start Link1 receive DMA

	idle;;								// once DMA is completed an interrupt is generated which brings out of idle and jumps to _dma_int

	xr4 = link_data_rx2;;				// xr4 = source index
	DC4 = xr7:4;;						// start Link1 transmit DMA						
	idle;;								// once DMA is completed an interrupt is generated which brings out of idle and jumps to _dma_int

_end_loop:
	jump _end_loop;nop;nop;nop;;

_dma_int:								// Once tx and rx DMA's are completed an interrupt is generated. This is the isr
	nop;;
	nop;;
	nop;;
	rti(ABS);nop;nop;nop;;