# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c8SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Direct_Digital_Synthesizer family Xilinx,_Inc. 5.0# END Select# BEGIN ParametersCSET output_frequencies=0.0CSET pipelined=trueCSET create_rpm=falseCSET phase_offset_angles=0.0CSET phase_increment=ProgrammableCSET spurious_free_dynamic_range=96.0CSET memory_type=AutoCSET sclr_pin=falseCSET clock_enable=falseCSET negative_sine=falseCSET outputs_required=Sine_and_CosineCSET phase_offset=ProgrammableCSET component_name=dds_moduCSET rdy_pin=falseCSET channels=1CSET noise_shaping=AutoCSET accumulator_latency=One_CycleCSET frequency_resolution=0.4CSET negative_cosine=falseCSET channel_pin=falseCSET dds_clock_rate=100.0CSET rfd_pin=falseCSET aclr_pin=false# END ParametersGENERATE