# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c8SET speedgrade = -12SET simulationfiles = StructuralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = ngcSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Fast_Fourier_Transform family Xilinx,_Inc. 3.2# END Select# BEGIN ParametersCSET scaling_options=UnscaledCSET create_rpm=falseCSET ce=falseCSET run_time_configurable_transform_length=falseCSET output_data_width=25CSET output_ordering=Bit_Reversed_OrderCSET fast_phase_factor=falseCSET memory_options_data=Block_RAMCSET number_of_stages_using_block_ram_for_data_and_phase_factors=1CSET ovflo=falseCSET rounding_modes=TruncationCSET component_name=ofdm_fftCSET memory_options_phase_factors=Block_RAMCSET fast_butterfly=falseCSET transform_length=256CSET implementation_options=Radix_4_Burst_IOCSET fast_complex_mult=falseCSET sclr=falseCSET optimize_for_speed_using_xtreme_dsp_slices=falseCSET input_width=16CSET phase_factor_width=16# END ParametersGENERATE