# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c5SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = ngcSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Block_Memory_Generator family Xilinx,_Inc. 1.1# END Select# BEGIN ParametersCSET write_depth_a=1024CSET operating_mode_a=WRITE_FIRSTCSET operating_mode_b=WRITE_FIRSTCSET write_width_a=16CSET write_width_b=1CSET use_regcea_pin=falseCSET primitive=8kx2CSET memory_type=Single_Port_ROMCSET byte_size=9CSET disable_out_of_range_warnings=falseCSET use_regceb_pin=falseCSET remaining_memory_locations=0CSET use_byte_write_enable=falseCSET enable_a=Always_EnabledCSET enable_b=Always_EnabledCSET component_name=rom_sineCSET assume_synchronous_clk=falseCSET disable_collision_warnings=falseCSET algorithm=Minimum_AreaCSET fill_remaining_memory_locations=falseCSET register_output_of_memory_primitives=falseCSET use_ssra_pin=falseCSET read_width_a=16CSET read_width_b=1CSET register_output_of_memory_core=falseCSET output_reset_value_a=0CSET output_reset_value_b=0CSET load_init_file=trueCSET coe_file=E:/rom_sin.coeCSET use_ssrb_pin=falseCSET collision_warnings=ALL# END ParametersGENERATE