# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c5SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT CORDIC family Xilinx,_Inc. 3.0# END Select# BEGIN ParametersCSET compensation_scaling=No_Scale_CompensationCSET create_rpm=trueCSET aclr=falseCSET output_width=17CSET ce=trueCSET x_out=trueCSET iterations=0CSET phase_output=falseCSET coarse_rotation=falseCSET functional_selection=Square_RootCSET architectural_configuration=ParallelCSET pipelining_mode=MaximumCSET nd=falseCSET register_outputs=trueCSET y_out=falseCSET round_mode=Nearest_EvenCSET component_name=sqrtCSET data_format=UnsignedIntegerCSET synchronization_enable=No_OverrideCSET precision=0CSET sclr=trueCSET input_width=32CSET phase_format=RadiansCSET register_inputs=trueCSET rdy=false# END ParametersGENERATE