################################################################ Xilinx Core Generator version i+IP+122117# Date: Sun Sep 09 15:50:11 2007#################################################################  This file contains the customisation parameters for a#  Xilinx CORE Generator IP GUI. It is strongly recommended#  that you do not manually alter this file as it may cause#  unexpected and unsupported behavior.################################################################# BEGIN Project OptionsSET addpads = FalseSET asysymbol = TrueSET busformat = BusFormatAngleBracketNotRippedSET createndf = FalseSET designentry = VHDLSET device = xc4vsx35SET devicefamily = virtex4SET flowvendor = Foundation_iSESET formalverification = FalseSET foundationsym = FalseSET implementationfiletype = NgcSET package = ff668SET removerpms = FalseSET simulationfiles = BehavioralSET speedgrade = -12SET verilogsim = TrueSET vhdlsim = True# END Project Options# BEGIN SelectSELECT Multiplier family Xilinx,_Inc. 10.0# END Select# BEGIN ParametersCSET ccmimp=Distributed_MemoryCSET clockenable=falseCSET component_name=rmultiCSET constvalue=129CSET dynamic_constant_reload=falseCSET multiplier_construction=Use_MultsCSET multtype=Parallel_MultiplierCSET optgoal=SpeedCSET outputwidthhigh=31CSET outputwidthlow=0CSET pipestages=4CSET portatype=SignedCSET portawidth=16CSET portbtype=SignedCSET portbwidth=16CSET reloadable=falseCSET roundpoint=0CSET sclrcepriority=SCLR_Overrides_CECSET syncclear=falseCSET use_custom_output_width=falseCSET use_load_done=falseCSET userounding=falseCSET zerodetect=false# END ParametersGENERATE# CRC: cca2e784