# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = D:\work\ISE\c5SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Divider_Generator family Xilinx,_Inc. 1.0# END Select# BEGIN ParametersCSET aclr=falseCSET ce=falseCSET sclrce_priority=SCLR_overrides_CECSET remainder_type=RemainderCSET divisor_width=16CSET algorithm_type=FixedCSET clocks_per_division=1CSET exponent_bias=0CSET component_name=div16CSET fractional_width=16CSET latency=1CSET dividend_width=16CSET operand_sign=UnsignedCSET sclr=falseCSET mantissa_width=8CSET exponent_width=8# END ParametersGENERATE