# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = C:\work\ISE\c11SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Distributed_Memory_Generator family Xilinx,_Inc. 2.1# END Select# BEGIN ParametersCSET reset_qspo=falseCSET coefficient_file=no_coe_file_loadedCSET reset_qdpo=falseCSET dual_port_address=non_registeredCSET common_output_ce=falseCSET memory_type=srl16_basedCSET depth=16CSET ce_overrides=ce_overrides_sync_controlsCSET data_width=16CSET default_data=0CSET component_name=srl16_w16_d16CSET single_port_output_clock_enable=falseCSET qualify_we_with_i_ce=falseCSET common_output_clk=falseCSET default_data_radix=16CSET output_options=non_registeredCSET dual_port_output_clock_enable=falseCSET sync_reset_qspo=falseCSET input_options=non_registeredCSET input_clock_enable=falseCSET sync_reset_qdpo=false# END ParametersGENERATE