# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = C:\work\ISE\c11SET speedgrade = -12SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc4vsx35SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ff668SET createndf = FalseSET designentry = VHDLSET devicefamily = virtex4SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT RAM-based_Shift_Register family Xilinx,_Inc. 8.0# END Select# BEGIN ParametersCSET aclr=falseCSET ce=falseCSET cepriority=Sync_Overrides_CECSET asyncinitval=0000000000000000CSET depth=16CSET meminitfile=no_coe_file_loadedCSET shiftregtype=Fixed_LengthCSET component_name=shiftregCSET syncinitval=0000000000000000CSET defaultdata=0000000000000000CSET syncctrlpriority=Reset_Overrides_SetCSET defaultdataradix=2CSET sset=falseCSET asyncinitradix=2CSET optgoal=AreaCSET ainit=falseCSET sclr=falseCSET width=16CSET aset=falseCSET syncinitradix=2CSET readmiffile=falseCSET sinit=falseCSET reglastbit=false# END ParametersGENERATE